Universal Asynchronous Receiver/Transmitter (UART)
User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
295
14.2.17
REG_MON_BAUD_CTRL
Name:
Baud Rate Monitor Control Register
Size:
32 bits
Address offset:
0x0044
Read/write access:
read/write
31
30
29
28
27
…
10
9
RSVD
R_UPD_OSC_IN_
XTAL
R_CYCNUM_PERBIT_OSC
R/W
R/W
8
7
6
5
4
3
2
1
0
R_BIT_NUM_THRES
R_MON_BAUD
_EN
R/W
R/W
Bit
Name
Access
Reset
Description
31:30
RSVD
N/A
-
Reserved
29
R_UPD_OSC_IN_XTAL
R/W
0
Enable updating parameter R_CYCNUM_PERBIT_OSC when updating parameter
R_CYCNUM_PERBIT_XTAL.
28:9
R_CYCNUM_PERBIT_OSC R/W
0
Average OSC clock cycle number of one bit, for Rx path OSC clock.
Software sets the initial value, hardware updates it depending on the monitor
result.
8:1
R_BIT_NUM_THRES
R/W
0
Bit number threshold of one monitor period, to get the average clock cycles of
one bit, the max value is 127.
0
R_MON_BAUD_EN
R/W
0
Function enable of monitoring Rx baud
14.2.18
REG_MON_BAUD_STS
Name:
Baud Rate Monitor Status Register
Size:
32 bits
Address offset:
0x0048
Read/write access:
read/write
31
30
29
28
27
…
22
21
20
19
18
…
1
0
RSVD
RO_MON_TOTAL_BIT
RO_MON
_RDY
R_CYCNUM_PERBIT_XTAL
R
R
R/W
Bit
Name
Access
Reset
Description
31:29
RSVD
N/A
-
Reserved
28:21
RO_MON_TOTAL_BIT
R
0
Actually monitored bit number
20
RO_MON_RDY
R
0
Indicate that calculation of actual cycle number per bit is finished. It’s cleared
when R_MON_BAUD_EN is 0.
19:0
R_CYCNUM_PERBIT_XTAL R/W
0
Average fractional XTAL clock cycle number of one bit, for Rx path XTAL clock.
Software sets the initial value, and hardware updates it depending on the
monitor result.
14.2.19
REG_MON_CYC_NUM
Name:
Clock Cycle Monitored Register
Size:
32 bits
Address offset:
0x004C
Read/write access:
read-only
31
30
29
28
27
26
25
…
2
1
0
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2019-05-15 10:08:03
