NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858
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© NXP B.V. 2018. All rights reserved.
User manual
COMPANY PUBLIC
Rev. 1.4 — 14 May 2018
314514
61 of 345
combination of both (depending on the clock settings), is available. This signal can be
overridden using CLIF_PLL_CLK_IN_OK_BYPASS register.
7.3.1 Optimum divider settings for CLIF PLL
Table 50. Optimum divider settings for PLL1 and PLL2
Fin
[MHz]
n1
m1
p1
m2
p2
Fref1
(MHz)
Fcco1
(MHz)
Fref2
(MHz)
Fcco2
(MHz)
Fpll_clk
out
(MHz)
Fpll_clk
out2
(MHz)
27.12
4
68
46
44
32.522
13.56
922.1
20.05
881.99
13.56
27.12
7.4 Register overview and description
7.4.1 Clock generator register overview
Table 51. Clock generator register overview (base address 0x4001 0000)
Name
Address
offset
Width
(bits)
Access
Reset value
Description
CLKGEN_STATUS_REG
0000h
32
R
00000000h
CLKGEN status register
CLKGEN_HFO_XTAL_REG
0004h
32
R/W
00FFF001h
HFO and XTAL control register
CLKGEN_HFO_TRIM_REG
0008h
32
R/W
00000000h
HFO trimming value register
CLKGEN_USB_PLL_CONTROL_
REG
000Ch
32
R/W
00F90001h
PLL Global Control Register
CLKGEN_USB_PLL_MDEC_WO_
SOFTDEC_REG
0010h
32
R/W
00000000h
PLL M decoded divider ratio
when the soft decoder is not used
CLKGEN_USB_PLL_NDEC_PDE
C_WO_SOFTDEC_REG
0014h
32
R/W
00000000h
PLL N and P decoded divider
ratio when the soft decoder is not
used
CLKGEN_CLIF_PLL1_CONTROL_
REG
0018h
32
R/W
02E3B190h
CLIF PLL usage configurations
CLKGEN_CLIF_PLL2_CONTROL_
REG
001Ch
32
R/W
02E121E0h
CLF PLL usage configurations
CLKGEN_CLIF_PLL_GLOBAL_C
ONTROL_REG
0020h
32
R/W
000000C8h
CLIF PLL integration
configurations
CLKGEN_INPUT_CLOCK_DETEC
TOR_CONTROL_REG
0024h
32
R/W
0000100Dh
Input clock detector control
RESERVED
0028h
32
R/W
0000000Fh
Reserved
CLKGEN_CLOCK_PRESENCE_B
YPASS_REG
002Ch
32
R/W
00000000h
clock presence for CLIF PLL
Unused
0030h -
3FFFh
32
-
-
unused
