NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858
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User manual
COMPANY PUBLIC
Rev. 1.4 — 14 May 2018
314514
241 of 345
14.1.9.2 BAUDRATE_REG
This register is used to generate the I2C serial clock frequency. The default is 1MHz
serial clock frequency at input system clock Frequency of 27 MHz
Table 277. BAUDRATE_REG (address offset 0x0004)
Legend: * reset value; <= mandatory value
Bit
Symbol
Access
Value
Description
31:8
RESERVED
R
0x0000000*
reserved
7:0
BAUDRATE
R/W
0xF4*
BAUDRATE bit field is used for the I2C Serial Clock
Frequency calculation. For a detailed calculation,
refer to
Section 14.1.5
14.1.9.3 SDA_HOLD_REG
This register is used to set the SDA hold time (SDA generation with respect to the falling
edge on SCL). It must be set to 0x00 when operating in Fast-mode Plus (freq SCL> 400
kHz).
Table 278. SDA_HOLD_REG (address offset 0x0008)
Legend: * reset value; <= mandatory value
Bit
Symbol
Access
Value
Description
31:5
RESERVED
R
0x0000000*
reserved
4:0
SDA_HOLD
R/W
0x09*
SDA Hold time; For a detailed calculation refer to
Section 14.1.6
14.1.9.4 I2C_ADDRESS_REG
This register contains the I2C slave address of the device.
Table 279. I2C_ADDRESS_REG (address offset 0x000C)
Legend: * reset value; <= mandatory value
Bit
Symbol
Access
Value
Description
31:10
RESERVED
R
0x0000000*
reserved
9:0
SLAVE_ADDRESS
R/W
0x2A*
I
2
C Slave 7 bit or 10-bit address
14.1.9.5 FIFO_THRESHOLD_REG
This register is used to set the FIFO threshold level for interrupt request generation.
Table 280. FIFO_THRESHOLD_REG (address offset 0x0010)
Legend: * reset value; <= mandatory value
Bit
Symbol
Access
Value
Description
31:11
RESERVED
R
0x0000000*
Reserved
10:8
RXMODE_THRESHOLD
R/W
0x7*
FIFO Threshold level for Interrupt Request generation when
I
2
C Master is configured for I
2
C Reception mode.
7:3
RESERVED
R
0x0000000*
2:0
TXMODE_THRESHOLD
R/W
0x1*
FIFO Threshold level for Interrupt Request generation when
I
2
C Master is configured for I
2
C Transmission mode.
