NXP Semiconductors PN7360AUEV, User Manual

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NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
User manual
COMPANY PUBLIC Rev. 1.4 — 14 May 2018
314514
184 of 345
Bit Symbol Access Value Description
1 50 %
2 65 %
3 80 %
11:10 CM_MILLER_TAU R/W 0h – 3h Configuration bits for the time constant of the reference
generation in Miller demodulator
0* 8 µs (cap of 125 f)
1 2 µs (cap of 500 f)
2 5 µs (cap of 200 f)
3 Not allowed
9 INTERNAL_USE
[1]
R/W 0*-1 For internal use
8 INTERNAL_USE
[1]
R/W 0*-1 For internal use
7 INTERNAL_USE
[1]
R/W 0-1* For internal use
6 INTERNAL_USE
[1]
R/W 0*-1 For internal use
5 INTERNAL_USE
[1]
R/W 0*-1 For internal use
4 INTERNAL_USE
[1]
R/W 0*-1 For internal use
3 INTERNAL_USE
[1]
R/W 0*-1 For internal use
2 INTERNAL_USE
[1]
R/W 0*-1 For internal use
1:0 INTERNAL_USE
[1]
R/W 0h*-3h For internal use
[1] Bit-field are either set by HAL or use default value from CLIF EEPROM default settings
Table 232. CLIF_ANA_AGC_REG register (address 011Ch)
* = reset value
Bit Symbol Access Value Description
31:4 RESERVED R 0* Reserved
3 RESERVED R/W 0*, 1 Reserved always set to 0
2 AGC_PD R/W 0*-1 AGC power down
1:0 AGC_VREF_SEL R/W 0h*-3h Select the comparison reference voltage
0* V
ref
= 1.15 V which results in V
Rx
= 0.5 V
pp
1* V
ref
f = 1.4 V which results in V
Rx
= 1 V
pp
2* V
ref
= 1.5 V which results in V
Rx
= 1.2 V
pp
3* V
ref
= 1.6 V which results in V
Rx
= 1.4 V
pp
Table 233. CLIF_ANA_CLK_MAN_REG register (address 0120h)
* = reset value
Bit Symbol Access Value Description
31:7 RESERVED R 0* Reserved
6 INTERNAL_USE
[1]
R/W 0*, 1 For internal use
5 INTERNAL_USE
[1]
R/W 0*-1 For internal use
4 INTERNAL_USE
[1]
R/W 0*-1 For internal use
3 INTERNAL_USE
[1]
R/W 0*-1 For internal use
2:0 CLOCK_CONFIG_DLL_ALM R/W 0h*-7h Select DLL clock phase in 45°C steps.