NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858
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© NXP B.V. 2018. All rights reserved.
User manual
COMPANY PUBLIC
Rev. 1.4 — 14 May 2018
314514
308 of 345
Bit
Symbol
Access Reset
Value
Description
3:0
EOR_SET_ENABLE
W
0
1 - set enable for End of Reception in
buffer N (0<=N<=3) interrupt
0001 - set enable for EOR interrupt for RX
buffer 0
0010 - set enable for EOR interrupt for RX
buffer 1
0100 - set enable for EOR interrupt for RX
buffer 2
1000 - set enable for EOR interrupt for RX
buffer 3
0000 - no effect
HOSTIF_INT_STATUS_REG
This register is a collection of interrupt status commands. Writing 1 to this register does
set the corresponding Interrupt Request ENABLE flag. Writing 0 to this register has no
effect.
Table 350. HOSTIF_INT_STATUS_REG (address offset 0x3FE0)
Bit
Symbol
Access Reset
Value
Description
31:27
RESERVED
W
0
Reserved
26
HSU_RX_FER_STATU
S
W
0
HSU RX frame error interrupt
25
BUFFER_CFG_CHAN
GED_ERROR_STATU
S
W
0
Buffer configuration changed during use
interrupt
24
AHB_WR_SLOW_STA
TUS
W
0
Slow AHB during write operation interrupt
23
AHB_RD_SLOW_STA
TUS
W
0
Slow AHB during read operation interrupt
22
AHB_ERROR_STATU
S
W
0
Ahb_error (hresp=1, or address overflow)
interrupt
21
WATERLEVEL_REAC
HED_STATUS
W
0
Water level reached interrupt status
20:17
RX_BUFFER_OVERF
LOW_STATUS
W
0
0001 - maximum buffer size exceeded
interrupt status for RX buffer 0
0010 - maximum buffer size exceeded
interrupt status for RX buffer 1
0100 - maximum buffer size exceeded
interrupt status for RX buffer 2
1000 - maximum buffer size exceeded
interrupt status for RX buffer 3
16
CRC_NOK_STATUS
W
0
Data-link layer CRC error interrupt status
