NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858
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User manual
COMPANY PUBLIC
Rev. 1.4 — 14 May 2018
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13.6.2.7 Register ct_ucr21_reg/ct_ucr22_reg (UART Configuration Register 2)
This configuration register defines the reception and transmission settings.
This register is doubled: ct_ucr21_reg is dedicated to the full slot and ct_ucr22_reg is
dedicated to the auxiliary slot. Both registers share the same address, the selection is
done via bit IOauxen of register ct_ssr_reg.
Table 255. ct_ucr21_reg/ct_ucr22_reg (address 0018h) bit description
Bit
Symbol
Access
Reset
Value
Description
31:8
RESERVED
-
0
Reserved
7
wrdacc
R/W
0b
FIFO WoRD ACCess
When set to logic 1, the FIFO supports word (4 bytes) access (read and
write), access failure is indicated by bit wrdaccerr in register ct_usr2_reg.
When set to logic 0, the FIFO supports byte access (read and write).
6
FIFO flush
R/W
0b
FIFO flush
When set to logic 1, the FIFO is flushed whatever the mode (reception or
transmission) is. It can be used before any reception or transmission of
characters but not while receiving or transmitting a character.
It is reset to logic 0 by hardware after one
clk_ip
cycle.
5
disintaux
R/W
0b
DISable INTAUX
When set to logic 1 the bit INTAUXL in register ct_usr2_reg will not generate
interrupt.
4
disATRcounter
R/W
0b
DISable ATR counter
- Slot 1:
When set to logic 1, the bits EARLY and MUTE in register ct_usr1_reg will not
generate interrupt.
This bit should be set before activating.
- Slot AUX:
This bit is not available for the auxiliary slot (ct_ucr22_reg) since
ATR counter is dedicated to slot 1.
3
dispe
R/W
0b
DISable Parity Error interrupt bit
When set to logic 1, the parity is not checked in both reception and
transmission modes, the bit pe in register ct_usr1_reg will not generate
interrupt.
2
disft
R/W
0b
DISable Fifo Threshold interrupt bit
When set to logic 1 the bit ft in register ct_usr1_reg will not generate interrupt.
1
MAN BGT
R/W
0b
MANual BGT
When set to logic 1, BGT is managed by software, else by hardware.
