NXP Semiconductors PN7360AUEV, User Manual

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NXP Semiconductors
UM10858
PN7462 family HW user manual
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User manual
COMPANY PUBLIC Rev. 1.4 — 14 May 2018
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15.4.2.10 USB Interrupt enable register
Table 365. USB Interrupt enable register (address offset = 0x24)
Reset value: 0x00000000
Bit Symbol Value Description Reset
Value
Access
31:0 INT_EN If this bit is set and the corresponding USB interrupt status bit is set
a hardware interrupt is generated on the interrupt line indicated by
the corresponding USB interrupt routing bit. 0 R/W
15.4.2.11 USB set interrupt status register
Table 366. USB set interrupt status register (address offset = 0x28)
Reset value: 0x00000000
Bit Symbol Value Description Reset
Value
Access
31:0 SET_EN If firmware writes a one to one of these bits, the corresponding USB
interrupt status bit is set. When this register is read, the same value
as the USB interrupt status register is returned. 0 R/W
15.4.2.12 USB interrupt routing register
Table 367. USB interrupt routing register (address offset = 0x2C)
Reset value: 0x00000000
Bit Symbol Value Description Reset
Value
Access
31:0 ROUTE_INT
This bit can control on which hardware interrupt line the
interrupt will be generated:
0 R/W
0 IRQ interrupt line is selected for this interrupt bit
1 FIQ interrupt line is selected for this interrupt bit
15.4.2.13 USB configuration
Table 368. USB configuration (address offset = 0x30)
Reset value: see configuration values
Bit Symbol Value Description Reset
Value
Access
4:0 PHYSEP
Number of physical endpoints implemented in this design
(excluding the default control endpoint). E.g. a value of 2 in
this field indicates that the design contains the default control
endpoint plus one IN endpoint (EP1 – IN) and one OUT
endpoint (EP1 – OUT)
RO
5 SB
EP single buffer supported
RO
6 DB
EP double buffer supported
RO