NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858
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User manual
COMPANY PUBLIC
Rev. 1.4 — 14 May 2018
314514
158 of 345
Bit
Symbol
Access
Value
Description
3
RX_ACTIVE
R
0*, 1
This bit indicates activity of the RXDecoder. If 1 a data reception
is ongoing, otherwise the RXDecoder is in idle state.
2:0
TRANSCEIVE_STATE
R
0* - 5
These registers hold the command bits
0*
IDLE state
1
WaitTransmit state
2
Transmitting state
3
WaitReceive state
4
WaitForData state
5
Receiving state
6
WaitLoopBack state
7
LoopBack state
Table 189. CLIF_TRANSCEIVE_CONTROL_REG register (address 000Ch)
* = reset value
Bit
Symbol
Access
Value
Description
31:30
RESERVED
R
0
reserved
29:24
INTERNAL_USE
R/W
0* -
111111b
for internal use
xxxxx1
IDLE state enabled to trigger IRQ
xxxx1x
WaitTransmit state enabled to trigger IRQ
xxx1xx
Transmitting state enabled to trigger IRQ
xx1xxx
WaitReceive state enabled to trigger IRQ
x1xxxx
WaitForData state enabled to trigger IRQ
1xxxxx
Receiving state enabled to trigger IRQ
23:18
RESERVED
R
0
Reserved
17
INTERNAL_USE
R/W
0*, 1
for internal use
16
INTERNAL_USE
R/W
0*, 1
for internal use
15:8
TX_BITPHASE
R/W
0* - FFh Defines the number of 13.56 MHz cycles used for
adjustment of TX_wait to meet the FDT.
7
RESERVED
R
0
reserved
6
INTERNAL_USE
R/W
0*, 1
for internal use
5
INTERNAL_USE
D
0*, 1
for internal use
4
INTERNAL_USE
R/W
0*, 1
for internal use
3
INTERNAL_USE
R/W
0*, 1
for internal use
2
RX_MULTIPLE_ENABLE
R/W
0*, 1
If this bit is set to 1, the receiver is re-activated after the end
of a reception. A status byte is written to the RAM containing
all relevant status information of the frame.
Note: Data in RAM is word aligned therefore empty bytes of
a data Word in RAM are padded with 0x00 bytes. SW has to
calculate the correct address for the following frame.
