NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858
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© NXP B.V. 2018. All rights reserved.
User manual
COMPANY PUBLIC
Rev. 1.4 — 14 May 2018
314514
30 of 345
Table 29. NVIC register overview
Address
Name
Type
Reset
Description
0xE000E100
NVIC_ISER
RW
0x00000000
enables, or reads the enabled state
of one or more interrupts
0xE000E104-
0xE000E17F
Reserved
0xE000E180
NVIC_ICER RW
0x00000000
disables, or reads the enabled state
of one or more interrupts
0xE000E184-
0xE000E1FF
Reserved
0xE000E200
NVIC_ISPR RW
0x00000000
on writes, sets the status of one or
more interrupts to pending. On reads,
shows the pending status of the
interrupts.
0xE000E204-
0xE000E27F
Reserved
0xE000E280
NVIC_ICPR RW
0x00000000
On writes, clears the status of one or
more interrupts to pending. On reads,
shows the pending status of the
interrupts.
0xE000E300-
0xE000E3FC
Reserved
0xE000E400-
0xE000E41C
NVIC_IPRn
RW
0x00000000
sets or reads interrupt priorities
0xE000E420-
0xE000E43C
Reserved
Table 30. NVIC_IPRn bit assignments
Bits
Name
Function
[31:30]
PRI_N3
enables, or reads the enabled state of one or more interrupts
[29:24]
-
Reserved
[23:22]
PRI_N2
disables, or reads the enabled state of one or more interrupts
[21:16]
-
Reserved
[15:14]
PRI_N1
on writes, sets the status of one or more interrupts to pending. On reads,
shows the pending status of the interrupts.
[13:8]
-
Reserved
[7:6]
PRI_N0
on writes, clears the status of one or more interrupts to pending. On
reads, shows the pending status of the interrupts.
[5:0]
-
Reserved
