NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858
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User manual
COMPANY PUBLIC
Rev. 1.4 — 14 May 2018
314514
290 of 345
maintains logic low. The HOSTIF_STATUS_REG.TX_BUFFER_LOCK bit is cleared logic
low.
14.3.4.15 Storing erroneous RX frames
By default, the incoming frames are discarded by the buffer manager if it detects an
error. This is achieved by
not
setting bit RX<n>_DATA_READY in register
HOSTIF_DATA_READY_STATUS_REG. In parallel, the buffer manager sets the bit
associated with the error event in register HOSTIF_INT_STATUS in order to signal an
interrupt to the CPU. If one of the following errors occurs when a frame is received, it
may still be stored in the RX buffer such that they may be analyzed for debug.
•
Frame underflow
•
Frame overflow
•
CRC error
This mode is enabled by setting bit STORE_RX_ERROR_FRAMES in register
HOSTIF_CONTROL_REG.
HOSTIF_DATA_READY_STATUS_REG.RX<n>_DATA_READY will be set logic high
even when the received frame contains an error. The interrupt associated with the error
type is also still generated. An EOR event is not generated. The EOR_STATUS flag in
register HOSTIF_INT_STATUS_REG maintains logic low. This feature is not applicable
in native mode since none of the above error conditions can be detected.
14.3.4.16 Sending frames directly from the CLIF RX buffer (“direct copy”)
Due to the fact that the HDLL frame payload is stored word-aligned in the buffers, with
the first word in buffer reserved for the header bytes, the frame data can be transferred
directly from one interface to another without an intermediate copy.
In order to send out a frame via host interface whose payload is that of a frame
previously received via the CLIF, the firmware must configure the start address of the
host interface TX buffer to be the same as the CLIF RX buffer. Once the frame has been
received, the firmware only needs to update the first word in the buffer to convert the
CLIF frame header to the HDLL header for host interface communication. The direct
copy is not applicable in native mode since the frame format is unknown a priori.
14.3.5 Host Interface register overview and description
14.3.5.1 Register overview
Table 322. Register overview (base address 0x4002 0000)
Name
Address
offset
Width
(bits)
Access Reset
value
Description
HOSTIF_STATUS_REG
0000h
32
R
00000000 Status
HOSTIF_CONTROL_REG
0004h
32
R/W
0017ff80
Buffer manager control
HOSTIF_HEADER_CONTRO
L_REG
0008h
32
R/W
00000520 Header description control
