NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858
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User manual
COMPANY PUBLIC
Rev. 1.4 — 14 May 2018
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271 of 345
treated as a Host Read and the Host Interface transmits the required data bytes on
MISO. All other values of the first byte are treated as an invalid access and the Host
Interface transmits FFh on MISO.
illustrates these three types of accesses.
Fig 59. SPI HDLL mode examples
14.3.2.5
NCI Mode
The NCI mode described in this section is a low-level protocol not to be confused with
the
NFC Controller Interface (NCI)
. The SPI can support NCI with and without CRC,
which determines the format of the transport bytes. When the CRC is not being used
(fields NCI_CRC_DISABLE and NCI_LENGTH_MODE both logic low in register
HOSTIF_CONTROL_REG), the same transport direction detector bytes are used (e.g. if
the first bit is logic low then it is a Host Write; otherwise for a Host Read, the MISO is set
to 0xFF. If the CRC is included in the protocol (fields NCI_CRC_DISABLE and
NCI_LENGTH_MODE both logic high in register HOSTIF_CONTROL_REG), then there
is no transport direction detector byte for a Host Write. The Host Read is indicated by the
first byte on MISO being 0xFF.
14.3.2.6
Native Mode
The Native mode supports full duplex transfer. Therefore, a Data Request and Data
Ready
pulse can occur after a short time. Please refer to the timing diagram in
Note that the host, which is always the master, is responsible for ensuring that the length
of the TX frame is exactly equal to the RX frame. If this is not the case, then the rising
edge of SPI Slave Select
in response to the shorter frame (or fragment) would truncate
the longer frame.
