NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
User manual
COMPANY PUBLIC
Rev. 1.4 — 14 May 2018
314514
187 of 345
Bit
Symbol
Access
Value
Description
17:16 INTERNAL_USE
R/W
0*-3h
For internal use
0*
Proportional: 2^(-3) and Integral: 2^(-20)
1
Proportional: 2^(-4) and Integral: 2^(-21)
2
Proportional: 2^(-5) and Integral: 2^(-22)
3
Proportional: 2^(-6) and Integral: 2^(-23)
15:14 RESERVED
R
0
Reserved
13:12 INTERNAL_USE
R/W
0*-3h
For internal use
0*
~37.8 us
1
~75.5 us
2
~151 us
3
~300 us
11
RESERVED
R
0
Reserved
10:8 INTERNAL_USE
R/W
0*-7h
For internal use
0*
2^(-10)
7
2^(-17)
7
RESERVED
R
0
Reserved
6:4
INTERNAL_USE
R/W
0*-7h
For internal use
0*
2^(-3)
7
2^(-10)
3:2
RESERVED
R
0
Reserved
1:0
RESERVED
R/W
0*-3h
Reserved
[1] Bit-field are either set by HAL or use default value from CLIF EEPROM default settings
Table 237. CLIF_INT_CLR_ENABLE_REG register (address 3FD8h)
* = reset value
Bit
Symbol
Access
Value
Description
31:30
RESERVED
W
0
Reserved
29
AGC_RFOFF_DET_
IRQ_CLR_ENABLE
W
0, 1
Writing 1 to this register does clear the corresponding IRQ
ENABLE flag
28
TX_DATA_REQ_IRQ_CLR_E
NABLE
W
0, 1
Writing 1 to this register does clear the corresponding IRQ
ENABLE flag
27
RX_DATA_AV_IRQ_CLR_EN
ABLE
W
0, 1
Writing 1 to this register does clear the corresponding IRQ
ENABLE flag
26
RX_BUFFER_OVERFLOW_I
RQ_CLR_ENABLE
W
0, 1
Writing 1 to this register does clear the corresponding IRQ
ENABLE flag
25
TX_WATERLEVEL_IRQ_CLR
_ENABLE
W
0, 1
Writing 1 to this register does clear the corresponding IRQ
ENABLE flag
24
RX_WATERLEVEL_IRQ_CLR
_ENABLE
W
0, 1
Writing 1 to this register does clear the corresponding IRQ
ENABLE flag
23
RESERVED
W
0
Reserved
