NXP Semiconductors PN7360AUEV, User Manual

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NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
User manual
COMPANY PUBLIC Rev. 1.4 — 14 May 2018
314514
129 of 345
Name Address
offset
Width
(bits)
Access Reset value Description
TIMERS_WDOG_INT_SET_STATUS_REG 3FD4h 32 W 00000000h Watchdog set interrupt
TIMERS_INT_CLR_ENABLE_REG 3FD8h 32 W 00000000h Timer clear interrupt enable
TIMERS_INT_SET_ENABLE_REG 3FDCh 32 W 00000000h Timer set interrupt enable
TIMERS_INT_STATUS_REG 3FE0h 32 R 00000000h Timer interrupt status
TIMERS_INT_ENABLE_REG 3FE4h 32 R 00000000h Timer interrupt enable
TIMERS_INT_CLR_STATUS_REG 3FE8h 32 W 00000000h Timer clear interrupt
TIMERS_INT_SET_STATUS_REG 3FECh 32 W 00000000h Timer set interrupt
RESERVED 3FF0h -
3FFCh 32 R 00000000h Reserved
11.4.2 Register description
Table 150. TIMERS_TIMER0_CONTROL_REG (address offset 0x0000)
Bit Symbol Reset Value Access Type Description
31:1 RESERVED 0 R Reserved
0 TIMER0_MODE 0 R/W 0 – single shot
1 – free running
Table 151. TIMERS_TIMER0_TIMEOUT_REG (address offset 0x0004)
Bit Symbol Reset Value Access Type Description
31:12 RESERVED 0 R Reserved
11:0 TIMER0_TIMEOUT 0 R/W Initial count value of Timer0 in step size of
0.30 ms
[2]
. If set to 0, this feature is disabled.
Table 152. TIMERS_TIMER0_COUNT_REG (address offset 0x0008)
Bit Symbol Reset Value Access Type Description
31:12 RESERVED 0 R Reserved
11:0 TIMER0_COUNT 0 R Current count value of Timer0 in step size of
0.30ms
Table 153. TIMERS_TIMER1_CONTROL_REG (address offset 0x000C)
Bit Symbol Reset Value Access Type Description
31:2 RESERVED 0 R Reserved
1 ENABLE_TIMER0_TRIGGER 0 R/W 1- Timer1 will decrement once when Timer0
reaches its terminal count (assuming that
field TIMER1_TIMEOUT is non-zero in
register TIMERS_TIMER1_TIMEOUT)
0: Timer1 counts independently