NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
User manual
COMPANY PUBLIC
Rev. 1.4 — 14 May 2018
314514
329 of 345
15.4.2.9 USB Interrupt status register
Table 364. USB Interrupt status register (address offset = 0x20)
Reset value: 0x00000000
Bit
Symbol
Description
Reset
Value
Access
0
EP0OUT
Interrupt status register bit for the Control EP0 OUT direction. This bit will be
set if NBytes transitions to zero or the skip bit is set by firmware or a SETUP
packet is successfully received for the control EP0. If the IntOnNAK_CO is
set, this bit will also be set when a NAK is transmitted for the Control EP0
OUT direction. Firmware can clear this bit by writing a one to it.
0
R/W/C
1
EP0IN
Interrupt status register bit for the Control EP0 IN direction. This bit will be
set if NBytes transitions to zero or the skip bit is set by firmware. If the
IntOnNAK_CI is set, this bit will also be set when a NAK is transmitted for
the Control EP0 IN direction. Firmware can clear this bit by writing a one to
it.
0
R/W/C
2
EP1OUT
Interrupt status register bit for the EP1 OUT direction. This bit will be set if
the corresponding Active bit is cleared by hardware. This is done in case the
programmed NBytes transitions to zero or the skip bit is set by firmware. If
the IntOnNAK_AO is set, this bit will also be set when a NAK is transmitted
for the EP1 OUT direction. Firmware can clear this bit by writing a one to it.
0
R/W/C
3
EP1IN
Interrupt status register bit for the EP1 IN direction. This bit will be set if the
corresponding Active bit is cleared by hardware. This is done in case the
programmed NBytes transitions to zero or the skip bit is set by firmware. If
the IntOnNAK_AI is set, this bit will also be set when a NAK is transmitted
for the EP1 IN direction. Firmware can clear this bit by writing a one to it.
0
R/W/C
…
28
EP14OUT
Interrupt status register bit for the EP14 OUT direction. This bit will be set if
the corresponding Active bit is cleared by hardware. This is done in case the
programmed NBytes transitions to zero or the corresponding skip bit is set
by firmware. If the IntOnNAK_AO is set, this bit will also be set when a NAK
is transmitted for the EP14 OUT direction. Firmware can clear this bit by
writing a one to it.
0
R/W/C
29
EP14IN
Interrupt status register bit for the EP14 IN direction. This bit will be set if the
corresponding Active bit is cleared by hardware. This is done in case the
programmed NBytes transitions to zero or the corresponding skip bit is set
by firmware. If the IntOnNAK_AI is set, this bit will also be set when a NAK is
transmitted for the EP14 IN direction. Firmware can clear this bit by writing a
one to it.
0
R/W/C
30
FRAME_INT
Frame interrupt. This bit is set to one every millisecond when the
VbusDebounced bit and the DCON bit are set. This bit can be used by
software when handling the isochronous endpoints. Firmware can clear this
bit by writing a one to it.
0
R/W/C
31
DEV_INT
Device status interrupt. This bit is set by hardware when one of the device
status change bits is set. Firmware can clear this bit by writing a one to it.
0
R/W/C
