NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858
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User manual
COMPANY PUBLIC
Rev. 1.4 — 14 May 2018
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244 of 345
14.1.9.10 TX_DATA
This register is used to fill the FIFO with the data to be transmitted & accessible as write
only registers, if the I2C Master is configured for transmission.
Table 285. TX_DATA (address offset 0x0040 to 0x004C)
Legend: * reset value; <= mandatory value
Bit
Symbol
Access
Value
Description
31:0
TX_DATA
W
0x0000000*
Data to be transmitted
1. The TX_DATA register fields are accessible as write-only during I2C master
configured as I2C transmitter. (IP_MODE = 0x0 in CONFIG_REG)
2. The Data written to TX_DATA register fields are considered to be WORD size,
however the byte granularity will be interpreted by the BYTECOUNT_CONFIG_REG
register.
3. The TX_DATA from offset address 0x0040 to 0x004C, is order independent. The TX
data can be written to any of these offset address 0x0040 or 0x0044 or 0x0048 or
0x004C in any order.
14.1.9.11 RX_DATA
This register is used to read the received data from FIFO & accessible as read only
registers if the I2C Master is configured for reception.
Table 286. RX_DATA (address offset 0x0050 to 0x005C)
Legend: * reset value; <= mandatory value
Bit
Symbol
Access
Value
Description
31:0
RX_DATA
R
0x0000000*
Data received
1. The RX_DATA register fields are accessible as read-only during I2C master
configured as I2C receiver. (IP_MODE = 0x1 in CONFIG_REG)
2. The Data from RX_DATA register fields are considered to be WORD size, however
the byte granularity will be interpreted by the BYTECOUNT_CONFIG_REG register.
3. The RX_DATA from offset address 0x0050 to 0x005C, is order independent. The RX
data can be read in any of these offset address 0x0050 or 0x0054 or 0x0058 or
0x005C in any order.
