NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858
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© NXP B.V. 2018. All rights reserved.
User manual
COMPANY PUBLIC
Rev. 1.4 — 14 May 2018
314514
304 of 345
[1] Can be overwritten by FW using either register HOSTIF_SET_DATA_READY_REG or register
HOSTIF_CLR_DATA_READY_REG.
[2] The buffer manager can only clear this bit.
[3] The buffer manager can only set this bit.
HOSTIF_DBG_RX_REG
This register is used for the debug received data.
Table 346. HOSTIF_DBG_RX_REG (address offset 0x0074)
Bit
Symbol
Access Reset
Value
Description
31:5
RX_REG
R
0
Contains byte the last received bytes to be
written into memory as one word
HOSTIF_DBG_RX_REG
This register is used to indicate the debug receive address.
Table 347. HOSTIF_DBG_RX_ADDR_REG (address offset 0x0078)
Bit
Symbol
Access Reset
Value
Description
31:16
RESERVED
R
0
Reserved
15:14
WR_PTR
R
0
Pointer to next byte to write into RX_REG
(next byte inside word to write to memory)
13:0
WR_ADDR
R
0
Next AHB write address
HOSTIF_INT_CLR_ENABLE_REG
This register is a collection of clear interrupt enable commands. Writing 1 to this register
does set the corresponding Interrupt Request ENABLE flag. Writing 0 to this register has
no effect.
Table 348. HOSTIF_INT_CLR_ENABLE_REG (address offset 0x3FD8)
Bit
Symbol
Access Reset
Value
Description
31:27
RESERVED
W
0
Reserved
26
HSU_RX_FER_CLR_
ENABLE
W
0
1 - clear enable for HSU RX frame error
interrupt0 - no effect
25
BUFFER_CFG_CHAN
GED_ERROR_CLR_E
NABLE
W
0
1 - clear enable for buffer config changed
during use interrupt
0 - no effect
24
AHB_WR_SLOW_CLR
_ENABLE
W
0
1 - clear enable for slow AHB during write
operation interrupt
0 - no effect
23
AHB_RD_SLOW_CLR
_ENABLE
W
0
1 - clear enable for slow AHB during read
operation interrupt
0 - no effect
