NXP Semiconductors PN7360AUEV User Manual Download

Page: 331 / 345

NXP Semiconductors

UM10858

PN7462 family HW user manual

UM10858

All information provided in this document is subject to legal disclaimers.

User manual
COMPANY PUBLIC

Rev. 1.4 — 14 May 2018

314514

331 of 345

Bit

Symbol

Value

Description

Reset

Value

Access

TREG

Toggle register available This indicates if the Data Toggle
debug register is reserved or not.

31:8

RESERVED

Reserved

15.4.2.14 USB endpoint toggle

Table 369. USB endpoint toggle (address offset = 0x34)

Reset value: 0x00000000

Bit

Symbol

Value

Description

Reset

Value

Access

29:0

TOGGLE

Endpoint data toggle: This field indicates the current value of
the data toggle for the corresponding endpoint.

31:30 RESERVED

Reserved

15.4.2.15 USB internal PLL

Table 370. USB internal PLL (address offset = 0x38)

Reset value: 0x00000000

Bit

Symbol

Value

Description

Reset

Value

Access

SEL_EXT_CLK

Select external crystal clock.

R/W

Internal PLL and RC circuit is selected as input clock for the
USB block

External clock input pin is selected as input clock for USB
block. The input clock must be 48MHz in this case.

31:3

RESERVED

Reserved

R/W

Summary of Contents for PN7360AUEV

Page 1: ...HW user manual Rev 1 4 14 May 2018 314514 User manual COMPANY PUBLIC Document information Info Content Keywords PN7462 PN7462 family PN7362 PN7360 NFC reader Abstract This document describes how to u...

Page 2: ...ore information please visit http www nxp com Revision history Rev Date Description 1 4 20180514 Editorial updates 1 3 20180212 Reworking the document to describe complete PN7462 family SDA hold equat...

Page 3: ...are equipped with 12 kB of SRAM data memory and 4 kB EEPROM All products within the family also include one host interface with either high speed mode I2C bus SPI USB or high speed UART and two master...

Page 4: ...D drop out Enhanced ESD protection 12 kV ISO IEC 7816 compliant EMVCo 4 3 compliant Clock generation up to 13 56 MHz Synchronous card support Possibility to extend the number of contact interfaces wit...

Page 5: ...to 20 MHz Clock management to enable low power consumption Memory Flash 160 kB RAM 12 kB EEPROM 4 kB 40 K boot ROM included including USB mass storage primary boot loader for code download Debug Optio...

Page 6: ...V Pad voltage supply external 3 3 V or 1 8 V or using an integrated LDO 3 3 V supply Integrated contact interface voltage regulation for 1 8 V 3 V and 5 V card supply including a DC to DC converter f...

Page 7: ...pitch ball grid array package 64 balls 4 5 mm x 4 5 mm x 0 80 mm SOT1307 2 PN7362AUHN HVQFN64 160 kB memory no contact interface no ISO IEC 7816 3 4 UART interface plastic thermal enhanced very thin q...

Page 8: ...user manual UM10858 All information provided in this document is subject to legal disclaimers NXP B V 2018 All rights reserved User manual COMPANY PUBLIC Rev 1 4 14 May 2018 314514 8 of 345 1 5 Block...

Page 9: ...user manual UM10858 All information provided in this document is subject to legal disclaimers NXP B V 2018 All rights reserved User manual COMPANY PUBLIC Rev 1 4 14 May 2018 314514 9 of 345 1 6 Block...

Page 10: ...HW user manual UM10858 All information provided in this document is subject to legal disclaimers NXP B V 2018 All rights reserved User manual COMPANY PUBLIC Rev 1 4 14 May 2018 314514 10 of 345 1 7 B...

Page 11: ...family incorporates several distinct memory regions Fig 4 shows the overall map of the entire address space from user program viewpoint following reset The APB peripheral area is 512 K in size and is...

Page 12: ...N7462 family HW user manual UM10858 All information provided in this document is subject to legal disclaimers NXP B V 2018 All rights reserved User manual COMPANY PUBLIC Rev 1 4 14 May 2018 314514 12...

Page 13: ...345 2 2 On chip flash memory map The PN7462 family contains 160 kB or 80 kB PN7360 on chip flash program memory The flash can be programmed using In System Programming ISP or In Application Programmi...

Page 14: ...this document is subject to legal disclaimers NXP B V 2018 All rights reserved User manual COMPANY PUBLIC Rev 1 4 14 May 2018 314514 14 of 345 2 3 EEPROM memory map The PN7462 family embeds 4 kB of on...

Page 15: ...document is subject to legal disclaimers NXP B V 2018 All rights reserved User manual COMPANY PUBLIC Rev 1 4 14 May 2018 314514 15 of 345 2 4 SRAM memory map The PN7462 family contains a total of 12...

Page 16: ...write transfer coming from the CPU Full page has to be written for flash Programming the Flash meaning copying the content of the page into the relevant EEPROM flash Implementing security bits at boo...

Page 17: ...Area 0x0020_2000 0x0020_2FFF UNDEFINED area 0x0020_3000 0x0022_AFFF 160 kBytes flash area 3 4 EEPROM controller 3 4 1 Write operation Write operation cannot be handled within one AHB clock cycle there...

Page 18: ...write operation cannot be handled within one AHB clock cycle therefore wait states are inserted by the AHB Slave Interface during page register write phase The following table gives an overview of min...

Page 19: ...EE_CRC_DAT_ADDR 0014h 32 R W 0FFF_0000h EEPROM CRC start end Addresses EE_CRC_1_COD_INIT 0018h 32 R W FFFF_FFFFh FLASH_1 CRC init value EE_CRC_1_COD 001Ch 32 R FFFF_FFFFh FLASH_1 CRC value EE_CRC_1_CO...

Page 20: ...OD R W 0 Block mode for FLASH_1 12 BNWSENS_1_COD R W 0 voltage drop sensor enable for FLASH_1 11 SKIPPRG_1_COD R W 0 skip program if erase fails for FLASH_1 10 STOP_1_COD R W 0 stop ramp up at low pow...

Page 21: ..._rst_dat W 0 resets the EEPROM Controller 2 crc_clear_dat W 0 CRC Clear Function for the EEPROM 1 full_dump_read_dat W 0 performs a full or partial read of the EEPROM with CRC calculation 0 prog_dat W...

Page 22: ...r output signal for FLASH_1 15 VMPOK_1_COD R 0 margin voltage flag for FLASH_1 14 prog_1_COD R 0 indicator if programming is ongoing for the FLASH_1 13 hverr_1_COD R 0 HV error signal for the FLASH_1...

Page 23: ...AR_1_COD is high meaning that FLASH_1 CRC must be set before CRC_CLEAR_1_COD Table 14 EE_CRC_1_COD address offset 0x001Ch Bit Symbol Access Value Description 31 0 ee_crc_1_COD R FFFFh FLASH_1 CRC valu...

Page 24: ...ponding to a native 32 bit data access AHB memory map divided by 8 Table 20 EE_TRIMM address offset 0x003Ch Bit Symbol Access Value Description 31 24 RESERVED 0 Reserved 23 20 hvtrimw_1_COD R W 0 HV t...

Page 25: ...rrupt clear enable command Table 23 EE_INT_SET_ENABLE address offset 0x0FDCh Bit Symbol Access Value Description 31 10 Reserved 0 Reserved 9 EE_ECC_READ_NOT_CORRE CT_1_COD_INT_SET_ENABLE W 0 FLASH_1 n...

Page 26: ...cod_completed_int_ STATUS R 0 FLASH_0 programming completed interrupt status variable 0 ee_prog_dat_completed_int_ST ATUS R 0 EEPROM programming completed interrupt status variable Table 25 EE_INT_ENA...

Page 27: ...S W 0 FLASH_1 programming completed interrupt clear status command 1 ee_prog_0_cod_completed_int_ CLR_STATUS W 0 FLASH_0 programming completed interrupt clear status command 0 ee_prog_dat_completed_in...

Page 28: ...iority levels with hardware priority level masking Non mask able interrupt NMI connected to the watchdog interrupt Software interrupt generation 4 2 Interrupt sources The following table lists the int...

Page 29: ...high level low interrupt as programmed GPIO 8 22 PCR interrupt rise fall both edge level high level low interrupt as programmed GPIO 9 23 PCR interrupt rise fall both edge level high level low interru...

Page 30: ...pending status of the interrupts 0xE000E204 0xE000E27F Reserved 0xE000E280 NVIC_ICPR RW 0x00000000 On writes clears the status of one or more interrupts to pending On reads shows the pending status of...

Page 31: ...ebugging of ROM service APIs and Boot code results into System reset Breakpoint and single step debugging is only allowed in the customer Application area 4 4 3 Hardware connection of SWD For using SW...

Page 32: ...e value 0x7 which enables the SysTick timer and the SysTick timer interrupt The following example illustrates selecting the SysTick timer reload value to obtain a 10 ms time interval with the system c...

Page 33: ...connected to VDD and buffered with 1 F capacitor to GND The SPI I C master interface requires additional supply PVDD_M_IN Fig 10 shows the power supply of the chip VBUS including the supply of the di...

Page 34: ...to use the PN7462 family as contactless reader the following voltages need to be supplied VBUS PVDD_IN if PVDD_OUT is not used it needs to be shorted to GND TVDD_IN If supplied by TVDD_OUT VUP_TX need...

Page 35: ...left floating and needs to be at the same voltage as the TVDD_IN pin 1 Using the PN7462 family s TXLDO 2 Without using PN7462 family s TXLDO The capacitance value must be chosen so that the capacitan...

Page 36: ...1 F capacitor to GND For SPI I C master interface following supply is also needed PVDD_M_IN The contact interface is powered through VBUSP which is connected to VBUS as shown on the schematic in Fig 1...

Page 37: ...14514 37 of 345 Fig 13 Powering the contact interface Fig 14 Contact interface power supply connection when the contact interface is not used aaa 021 145 SCVDD VBUSP VBUS VDDP VBUS IDDP VBUS GDNP SAM...

Page 38: ...o prevent the IC from overheat current overconsumption and overloading the DC to DC converter For the RF transmitter stage a separated low drop output regulator is embedded This module also integrates...

Page 39: ..._OUT O can be set in PMU_TXLDO_CONTROL_ REG 38 VUP_TX I externally powered or VBUS 39 VDD O 1 8 V output for DVDD 43 VBUS I Externally powered 44 PVDD_OUT O 3 3V output If connected to GND PVDD_IN is...

Page 40: ...mily basic schematic 6 2 1 Low Drop Out regulators The PMU embeds several Low Drop Out regulators LDO in order to ensure the stability of the power supply 6 2 1 1 Main LDO The Main LDO MLDO provides 1...

Page 41: ...a constant output voltage for the RF interface The TXLDO is designed to protect the chip from voltage ripple introduced by the power supply on the VUP_TX pin It is powered through VUP_TX pin The prog...

Page 42: ...the PN7462 family is used in the system as the gateway to configure all modes of supply for the product using the control registers Note that additional registers related to PMU control are located in...

Page 43: ...emperature sensors associated with the contactless TXLDO and the contact DC to DC converter interfaces The main purpose of these sensors is to monitor the temperature and prevent the overheating which...

Page 44: ...tus of the VBUS2 monitor is available in the status register The software has to check whether the voltage is sufficient before enabling the LDO The PVDD LDO can be enabled when the input supply VBUS2...

Page 45: ...R W 0400_0000h TXLDO control register PMU_LDO_CONTR OL_REG 000Ch R W 0000_0000h DC to DC converter control register INTERNAL_USE 1 00010h R W 0000_0000h For internal use INTERNAL_USE 1 0014h R W 0000_...

Page 46: ...USP monitor 1 VBUSP value is greater than threshold 20 POK_VBUSMON2 R 0x00 Output of VBUS monitor2 1 VBUS2 value is greater than threshold 19 POK_PVDDOUT R 0x00 Output of PVDD monitor 1 PVDDOUT is ok...

Page 47: ...x00 Sets threshold for VBUS MON2 0 2 5 V 1 4 V 6 ENABLE_VBUSPMON R W 0x00 Activates VBUSP monitor 1 Enable VBUSP monitor 0 Disable VBUSP monitor 5 ENABLE_VBUSMON2 R W 0x00 Activates VBUS monitor 2 1 E...

Page 48: ...overcurrent detection 22 21 TXLDO_SELECT_ANT R W 0x00 Offset selection for detection range of the TXLDO_DET_OUT 0 20mA 1 50mA 2 70mA 3 100mA Measurement range of the 7 bit DAC with corresponding offs...

Page 49: ...R_EN R W 0x00 Activates the Current Detection for DAC current measurement manual mode 1 Enable current detection for TXLDO 0 Disable current detection for TXLDO 0 TXLDO_ENABLE R W 0x00 Enable the whol...

Page 50: ...s if set by software 3 DCDC_OVERLOAD_IRQ_CLEAR _ENABLE X 0x00 clears enable state of DC to DC converter overload Automatically cleared after 2 cycles if set by software 2 SCVDD_OVERLOAD_IRQ_CLEA R_ENA...

Page 51: ...ction of Interrupt Status commands Table 44 PMU_INTERRUPT_STATUS_REG address offset 0x3FE0 Bit Symbol Access Value Description 31 9 RESERVED R 0x00 Reserved 8 VBUSMON2_LOW_IRQ_STATUS R 0x00 Indicates...

Page 52: ...Automatically cleared after 2 cycles if by software 3 DCDC_OVERLOAD_IRQ_ENAB LE R 0x00 Indicates enabled DC to DC converter overload interrupt Automatically cleared after 2 cycles if by software 2 SCV...

Page 53: ...ensor interrupt Automatically cleared after 2 cycles if set by software 6 7 1 10 PMU_INTERRUPT_SET_STATUS_REG This register is a collection of Set Interrupt Status commands with automatic clear if set...

Page 54: ...ensor interrupt Automatically cleared after 2 cycles if set by software 6 7 2 TXLDO Register settings Table 48 TXLDO Register Mode Register Bit Field full power PMU_TXLDO_CONTROL_REG TXLDO_ENABLE 1 TX...

Page 55: ...k Loop Internal CLIF PLL Phase Lock Loop In addition to the clock sources the clock generator comprises a digital control unit which controls and monitors the signals coming from the clocks and integr...

Page 56: ...with the external quartz and the trimming capacitors shown in Fig 19 Table 49 summarizes the requirements for the crystals PN7462AU Fig 19 27 12 MHz crystal oscillator connection Table 49 Crystal req...

Page 57: ..._SPARE0 to 0 3 Wait for 4 clk_lfo clock cycles 4x 1 380 KHz 10 53 us 4 Clear CLKGEN_HFO_XTAL_REG XTALl_BYPASS to 0 5 Clear CLKGEN_HFO_XTAL_REG XTAL_SELECT_EXTERNAL_CLOCK to 0 6 Set XTAL_ENABLE_KICK to...

Page 58: ...wer in active more low power down current On Chip loop filter no external RC components needed 7 2 1 USB PLL Clock source selection The USB PLL input can be selected between Crystal oscillator output...

Page 59: ...N P 27 12 MHz 69 13 3 48 MHz CLKGEN_USB_PLL_CONTROL_REG usb_pll_mnp_sel 1 M 92 N 13 P 4 Clkout Clkinx M N P 27 12 MHz 92 13 4 47 9815 MHz The Soft Decoder can be bypassed in order to have the full con...

Page 60: ...CLKGEN_USB_PLL_CONTROL_REG USB_CLK_DETECT_ENABLE 0 8 Exit the PLL from the Power Down Mode CLKGEN_USB_PLL_CONTROL_REG PLL_PD 0 9 Enable the PLL CLKGEN_USB_PLL_CONTROL_REG PLL_CLKEN 1 10 Poll for CLKG...

Page 61: ..._STATUS_REG 0000h 32 R 00000000h CLKGEN status register CLKGEN_HFO_XTAL_REG 0004h 32 R W 00FFF001h HFO and XTAL control register CLKGEN_HFO_TRIM_REG 0008h 32 R W 00000000h HFO trimming value register...

Page 62: ..._OK R 0 PLL input clock detector ok signal 1 clk_in is present and correct 0 clk_in not ok 19 CLIF_PLL_LOCK2 R 0 Lock detector Output for 2nd PLL 1 PLL2 lock is set 0 PLL2 lock is not set 18 CLIF_PLL_...

Page 63: ...h bits Access Reset value Description CLKGEN_HFO_XTAL_REG 0004h 32 R W 00FFF001h HFO and XTAL control register CLKGEN_HFO_TRIM_REG 0008h 32 R W 00000000h HFO trimming value register 7 5 1 1 HFO and XT...

Page 64: ...Bypass XTAL 0 XTAL not Bypassed 1 XTAL_CONTROL_SW R W 0x00 high to control the XTAL oscillator by SW 1 Enable software control of XTAL oscillator 0 Disable software control of XTAL oscillator 0 HFO_EN...

Page 65: ...SB_PLL_CONTROL_REG address 000Ch Bit Symbol Access Value Description 31 RESERVED R W 0x00 Reserved 30 USB_PLL_MNPSEL R W 0x00 M N P selection values for the Soft Decoder 0 M 600 N 113 P 3 1 M 92 N 13...

Page 66: ...pass of USB_PLL post divider 0 USB_PLL post divider Bypass disable 3 USB_PLL_DIRECTI R W 0x00 Bypass of the USB_PLL pre divider 1 Enable Bypass of USB_PLL pre divider 0 USB_PLL pre divider Bypass disa...

Page 67: ...tion CLIF PLL is controlled by the registers shown in Table 60 More detailed descriptions follow Writes to any unused bits are ignored A read of any unused bits will return a logic zero Warning Improp...

Page 68: ...0x00 1 Enable functional CLIF_PLL test chain of lock detector 1 0 CLIF_PLL_FUNC_TEST1_LOCK1 R W 0x00 1 Enable functional divider test of lock detector 1 7 7 2 CLIF PLL CONTROL2 REG The CLKGEN_CLIF_PLL...

Page 69: ...ll_clk_in detection 13 12 CLIF_PLL_REF_CLK_SELECT R W 0x00 Select the reference clock for CLIF PLL 00 Clk_input_buffer 01 clk_xtal 10 tie 0 11 tie 0 11 RESERVED R W 0x00 Reserved 10 CLIF_CLK_DETECT_EN...

Page 70: ...clk_in detection 12 5 INPUT_USB_CLOCK_EDGES_NUM BER R W 0x80 Defines the expected amount of input clock edges during the detection window length Default value is set to detect a 27 12 MHz input clock...

Page 71: ...al startup of the PN7462 family and manages the behavior of the system in low power and active modes The PCR unit is the only digital block that is powered in the standby mode The PCR unit provides fo...

Page 72: ...debug interface Software ARM Software reset from the ARM processor Resets the whole chip except the PCR and the ARM debug interface I2C interface I2C Standard 3 0 defines a method to reset the chip vi...

Page 73: ...the boot block At that point all of the processor and peripheral registers have been initialized to predetermined values 8 2 Boot reason decoding Table 67 Boot reason decoding PCR_STATUS boot_reason...

Page 74: ...er mode default or shut down mode The standby mode is triggered by the application firmware Before entering the standby mode the PN7462 family executes automatically the deactivation of the contact ca...

Page 75: ...d for wake up 8 No host interface is selected 9 GPIO interrupt found 10 TVDD voltage has risen above 5 V 11 Card insertion or removal detected 12 Contact unart int_aux pin has given an interrupt 13 Co...

Page 76: ...8 V triggers wake up Always active RF level detection caused by activity on the CLIF interface e g by bringing card near to CLIF Temperature sensor threshold reached when the temperature goes below th...

Page 77: ...2018 314514 77 of 345 LDO PLL Active Standby Suspend HPD Hardware Software DCDC SCLDO VCCLDO Full Low power OFF OFF OFF enabling power switches software TXLDO Full Low power OFF Standby LDO mode Stand...

Page 78: ...314514 78 of 345 8 4 Clock box The Clock Box is responsible for generating all clock signals for the system The PCR_CLK_CFG_REG and PCR_CLK_CFG2_REG are used by firmware to gate system and IP clocks g...

Page 79: ...st purpose Others INVALID should not be programmed 8 5 Clock Gating In order to reduce the overall power consumption the PN7462 family enables adjusting the system clock and integrates clock gating me...

Page 80: ...nnected to a specific peripheral function Dynamic configuration as inputs or outputs or analog by FW Pull up pull down or tri state configuration The GPIO read write are made by the firmware using sep...

Page 81: ...done by using configuration of PCR_SYS_REG hif_selection bits in PCR_SYS_REG register described in Table 75 8 7 Register overview Table 71 Register overview base address 0x4002 4000 Name Address Offs...

Page 82: ...a PCR_PAD_ATX_C_REG 0x0048 32 rw 0x00000000 host if pad i2c_adr0 spi_miso hsu_rts_n usb N A smbalert PCR_PAD_ATX_D_REG 0x004C 32 rw 0x00000000 host if pad i2cadr1 spi_sck hsu_cts_n usb N A smb N A PC...

Page 83: ...0x00C4 32 rw 0x00000008 TXLDO sequence management PCR_BOOT2_REG 0x00C8 32 rw 0x00000000 BOOT reason register extention PCR_GPREG3_REG 0x00CC 32 rw 0x00000000 general purpose register 3 for SW PCR_GPRE...

Page 84: ...ter 1 for SW Table 74 PCR_GPREG2_REG address offset 0x08 Bit Symbol Access Value Description 31 0 PCR_GPREG2 R W 0 general purpose register 2 for SW Table 75 PCR_SYS_REG address offset 0x0C Bit Symbol...

Page 85: ...011 HSU selected as host interface 100 USB selected as host interface others Invalid Table 76 PCR_PMU_REG address offset 0x10 Bit Symbol Access Value Description 31 29 PBF_CONST_LOAD_VA L rw 0x00 con...

Page 86: ...AS trim value 3 2 PVDDLDO_MODE rw 0x03 Selects pvddldo mode normal low power soft start power down 11 power down 10 soft start 01 low power mode 00 normal mode 1 0 RESERVED rw 0x00 Reserved Table 77 P...

Page 87: ...level detector Table 78 PCR_TEMP_REG address offset 0x18 Bit Symbol Access Value Description 31 26 RESERVED rw 0x00 Reserved 25 TEMP_ENABLE_CAL_1 rw 0x00 Enable calibration of temperature sensor 1 1 E...

Page 88: ...RFACE rw 0x00 1 Enable Wake up host interface Table 80 PCR_WAKEUP_CFG_REG address offset 0x20 Bit Symbol Access Value Description 31 23 RESERVED rw 0x00 Reserved 22 EN_ADV_RFLD rw 0x00 1 Enable advanc...

Page 89: ...x00 Indicator for more than 3 V at PVDD_M pin 1 PVDD_M is available and over 3 3 V 0 PVDD_M is not over 3 3 V 27 POK_PVDD_3V r 0x00 Indicator for more than 3V at PVDD pin 1 PVDD is available and over...

Page 90: ...ler automatic clock gating enable 0 EEPROM controller automatic clock gating disable 27 IPCLOCK_CTIF_ENABLE rw 0x00 1 Enable contact interface IP clock 0 Disable contact interface IP clock 26 IPCLOCK_...

Page 91: ...0 Disable clock source for CRC 14 CLOCK_CLKGEN_ENABLE rw 0x01 1 Enable clock source for CLKGEN 0 Disable clock source for CLKGEN 13 RESERVED rw 0x01 Set to 0 12 CLOCK_RNG_ENABLE rw 0x01 1 Enable clock...

Page 92: ...1 RESERVED 15 14 SPIM_IP_CLKSEL rw 0x00 Selects ip clock divider value for spim 00 xtal 1 01 xtal 2 10 xtal 4 11 RESERVED 13 12 I2CM_IP_CLKSEL rw 0x00 Selects ip clock divider value for spim 00 xtal 1...

Page 93: ...for GPIO10 20 PADIN_GPIO9 r 0x00 input value for GPIO9 19 PADIN_GPIO8 r 0x00 input value for GPIO8 18 PADIN_GPIO7 r 0x00 input value for GPIO7 17 PADIN_GPIO6 r 0x00 input value for GPIO6 16 PADIN_GPI...

Page 94: ...IO6 rw 0x00 output value for GPIO6 16 PADOUT_GPIO5 rw 0x00 output value for GPIO5 15 PADOUT_GPIO4 rw 0x00 output value for GPIO4 14 PADOUT_GPIO3 rw 0x00 output value for GPIO3 13 PADOUT_GPIO2 rw 0x00...

Page 95: ...pull down 1 ATX_B_EN_OUT rw 0x00 1 Enables output driver for ATX_B 0 ATX_B_EN_IN rw 0x00 1 Enables input driver for ATX_B Table 90 PCR_PAD_ATX_C_REG address offset 0x48 Bit Symbol Access Value Descri...

Page 96: ...ctive low signal 1 INT_AUX is active low 0 INT_AUX active high 6 INT_AUX_GPIOMODE_EN rw 0x00 Puts the INT_AUX PAD in GPIO mode By default in I2C mode 1 Enable GPIO mode for INT_AUX pads 0 INT_AUX pad...

Page 97: ...CLK_AUX pad in functional mode 5 CLK_AUX_SW_ENABLE rw 0x00 1 Enabling software register control for CLK_AUX 4 CLK_AUX_SLEW_RATE rw 0x00 Select driver strength for CLK_AUX 1 Enable Slew for CLK_AUX 3 2...

Page 98: ...00 Select driver strength for GPIO2 1 Enable slew for GPIO2 3 2 GPIO2_PUPD Rw 0x00 Enable pull Up Down on GPIO2 10 Enable pull up 11 Enable pull down 1 GPIO2_EN_OUT Rw 0x00 1 Enables output driver for...

Page 99: ...l up 11 Enable pull down 1 GPIO5_EN_OUT rw 0x00 1 Enables output driver for GPIO5 0 GPIO5_EN_IN rw 0x01 1 Enables input driver for GPIO5 Table 102 PCR_PADGPIO6_REG address offset 0x78 Bit Symbol Acces...

Page 100: ...cription 31 5 RESERVED rw 0x00 Reserved 4 GPIO9_SLEW_RATE rw 0x00 Select driver strength for GPIO9 1 Enable slew for GPIO9 3 2 GPIO9_PUPD rw 0x00 Enable pull Up Down on GPIO9 10 Enable pull up 11 Enab...

Page 101: ...pull up 11 Enable pull down 1 GPIO12_EN_OUT rw 0x00 1 Enables output driver for GPIO12 0 GPIO12_EN_IN rw 0x01 1 Enables input driver for GPIO12 Table 109 PCR_PADSWDIO_REG address offset 0x94 Bit Symb...

Page 102: ...offset 0xAC Bit Symbol Access Value Description 31 5 RESERVED rw 0x00 Reserved 4 RX_PROT_IDDQ rw 0x00 1 Set RX protection to power down for Iddq measurement 3 TXPROT_ENABLE_AUTO_ FREEZE rw 0x00 Enable...

Page 103: ...input 11 SPIM_SCK_EN_IN rw 0x00 SW control for SPIM_SCK ENZI ENZI EN_IN when SPIM_SW_ENABLE 1 1 SPIM CLK enabled as input 10 9 SPIM_MISO_EPUD rw 0x00 SW control for SPIM_MISO EPUD EPD when SPIM_SW_ENA...

Page 104: ...Description 31 24 RESERVED rw 0x00 Reserved 23 11 HSU_TX_CLK_CORRECT rw 0x00 clock correction for TX only save reg for stby 10 0 HSU_RX_CLK_CORRECT rw 0x00 Clock correction for RX only save reg for st...

Page 105: ...able 123 PCR_GPREG7_REG address offset 0xDC Bit Symbol Access Value Description 31 0 PCR_GPREG7 rw 0x00 general purpose register for SW Table 124 PCR_GPIO_INT_ACTIVE_LOW_REG address offset 0xE0 Bit Sy...

Page 106: ...dge 0 Active_high Rising edge 1 Active_low falling edge 1 GPIO2_INTR_ACTIVE_LO W rw 0x00 indicates if GPIO2 interrupts are active low falling edge 0 Active_high Rising edge 1Active_low falling edge 0...

Page 107: ...sensitive edge sensitive 0 Edge sensitive 1 Level sensitive 2 GPIO3_INTR_LEVEL_SEN SITIVE rw 0x00 indicates if GPIO3 interrupts are level sensitive edge sensitive 0 Edge sensitive 1 Level sensitive 1...

Page 108: ...h positive edge and negative edge triggered 5 GPIO6_INTR_BOTH_EDGE _SENSITIVE rw 0x00 indicates if GPIO6 interrupts are both positive and negative edge triggered 0 Not both edge triggered 1 Both posit...

Page 109: ...er To be set if normal RF Level detector is used for 1 Disable Pre Amplifier 17 16 ADV_RFLD_PREAMP_GAI N rw 0x00 gain setting for pre amplifier 15 12 ADV_RFLD_CLKREC_TIM E rw 0x00 boot up time for clo...

Page 110: ...able 1 Disable GPIO8 interrupt 22 GPIO7_PAD_HIGH_INT_CL R_ENABLE x 0x00 GPIO7 pad going high interrupt clear enable 1 Disable GPIO7 interrupt 21 GPIO6_PAD_HIGH_INT_CL R_ENABLE x 0x00 GPIO6 pad going h...

Page 111: ...rupt Table 131 PCR_INT_SET_ENABLE_REG address offset 0x3FDC Bit Symbol Access Value Description 31 28 RESERVED x 0x00 Reserved 27 GPIO12_PAD_HIGH_INT_S ET_ENABLE x 0x00 GPIO12 pad going high interrupt...

Page 112: ...ABLE x 0x00 PVDD current limiter active interrupt set enable 1 Enable PVDD current limiter interrupt 5 TEMPERROR1_INT_SET_ ENABLE x 0x00 Temperature error 1 interrupt set enable 1 Enable temperature s...

Page 113: ...rrupt status 1 Indicates GPIO1 interrupt is set 15 11 RESERVED r 0x00 Reserved 10 VBUSP_MON_HIGH_INT_S TATUS r 0x00 VBUSP monitor going high interrupt status 1 Indicates VBUSP monitor high interrupt i...

Page 114: ...IO5_PAD_HIGH_INT_E NABLE r 0x00 GPIO5 pad going high interrupt enable 1 Indicates GPIO5 interrupt enabled 19 GPIO4_PAD_HIGH_INT_E NABLE r 0x00 GPIO4 pad going high interrupt enable 1 Indicates GPIO4 i...

Page 115: ..._STATUS x 0x00 GPIO10 pad going high interrupt clear status 1 Clear GPIO10 interrupt Auto clear after 2 cycles 24 GPIO9_PAD_HIGH_INT_CL R_STATUS x 0x00 GPIO9 pad going high interrupt clear status 1 Cl...

Page 116: ...lear status 1 Clear temperature sensor 1 error interrupt Auto clear after 2 cycles 4 TEMPERROR0_INT_CLR_ STATUS x 0x00 Temperature error 0 interrupt clear status 1 Clear temperature sensor 0 error int...

Page 117: ...after 2 cycles 16 GPIO1_PAD_HIGH_INT_S ET_STATUS x 0x00 GPIO1 pad going high interrupt set status 1 Set GPIO1 interrupt Auto clear after 2 cycles 15 11 RESERVED x 0x00 Reserved 10 VBUSP_MON_HIGH_INT_...

Page 118: ...t AAL5 IEEE 802 3 standard with a generator polynomial of Note No final XOR is performed CRC calculation is performed in parallel meaning that one CRC calculation is performed in one clock cycle The s...

Page 119: ...lated CRC value e g preloaded value and W n the nth bit of the input data Step1 Implement a standard serial CRC calculation C_new 0 C_prev 3 xor W C_new 1 C_prev 0 xor C_prev 3 xor W C_new 2 C_prev 1...

Page 120: ...ompute the two matrices to generate the four equations for each CRC_new bit C_new 0 W 0 xor W 3 xor C_prev 0 xor C_prev 3 C_new 1 W 0 xor W 1 xor W 3 xor C_prev 0 xor C_prev 1 xor C_prev 3 C_new 2 W 1...

Page 121: ...he first 4 bytes of the buffer is written to CRC_DAT32 the next 2 bytes is written to CRC_DAT16 and the last byte is written to CRC_DAT8 The CRCDAT_CALC is returned that contains the computed CRC Alte...

Page 122: ...ata register for 16 AMBA bitstream CRC_DAT8_REG 0Ch 32 R W 00000000h CRC data register for 8 AMBA bitstream CRC_DAT_CALC_REG 10h 32 R 0000FFFFh CRC calculated value for CRC16 CRC32 CRC_DAT_PRELOAD_REG...

Page 123: ...eturns the currently addressed CRC byte see CRCCON Table 142 CRC_DAT8_REG address offset 0x0C Bit Symbol Access Value Description 31 8 RESERVED 0 Reserved 7 0 CRCDAT8 R W 0 1 for each bit 8 bits CRC v...

Page 124: ...a new seed into the PRNG 10 1 RNG features Combination of an analog TRNG and a digital PRNG 80 bit LFSR Substitution Box Dedicated clock for TRNG PRNG runs on system clock Data Ready Indicator bit Com...

Page 125: ...LFSR is The feedback polynomial is XOR with the TRNG input when a new seed is loaded Some bits in the LFSR feeds an S BOX lookup table taken from the DES Specification and the output of the SBOX is XO...

Page 126: ...7 3 RESERVED 0x00 Reserved 2 rng_ready R 0 1 a new RNG value is available 0 the current value of RNG_STATUS_REG rng is not random 1 rng_seed_error R 0 1 TRNG did not provide the random stream in time...

Page 127: ...ax delay s Chaining possible Timer 0 LFO 2 190 KHz 12 300 us 1 2 no Timer 1 LFO 2 190 KHz 12 300 us 1 2 yes Timer 2 HFO 20 MHz 32 50 ns 214 no Timer 3 HFO 20 MHz 32 50 ns 214 no Watchdog LFO 128 2 96...

Page 128: ...Timer0 TIMERS_TIMER1_CONTROL_REG 000Ch 32 R W 0000000h Control of Timer1 TIMERS_TIMER1_TIMEOUT_REG 0010h 32 R W 0000000h Timeout value of Timer1 TIMERS_TIMER1_COUNT_REG 0014h 32 R 0000000h Current cou...

Page 129: ...000h Reserved 11 4 2 Register description Table 150 TIMERS_TIMER0_CONTROL_REG address offset 0x0000 Bit Symbol Reset Value Access Type Description 31 1 RESERVED 0 R Reserved 0 TIMER0_MODE 0 R W 0 sing...

Page 130: ...scription 31 12 RESERVED 0 R Reserved 11 0 TIMER1_COUNT 0 R Current count value of Timer1 in step size of 0 30 ms Table 156 TIMERS_TIMER2_CONTROL_REG address offset 0x0018 Bit Symbol Reset Value Acces...

Page 131: ...ress offset 0x0030 Bit Symbol Reset Value Access Type Description 31 1 RESERVED 0 R reserved 0 WDOG_KICK 0 D 1 re initialize the Watchdog Timer to value WDOG_TIMEOUT 0 no effect Table 163 TIMERS_WDOG_...

Page 132: ...RESERVED 0 W reserved 0 WDOG_TIMEOUT_SET_STATUS 0 W 1 set Watchdog timeout interrupt 0 no effect Table 169 TIMERS_INT_CLR_ENABLE_REG address offset 0x3FD8 Bit Symbol Reset Value Access Type Descriptio...

Page 133: ...upt status 0 TIMER0_TIMEOUT_STATUS 0 R Timer0 timeout interrupt status Table 172 TIMERS_INT_ENABLE_REG address offset 0x3FE4 Bit Symbol Reset Value Access Type Description 31 4 RESERVED 0 R Reserved 3...

Page 134: ...iving and the receiver circuitry and all the low level functionalities to enable the realization of an NFC forum or an EMV compliant reader The PN7462 family allows different voltages for the RF drive...

Page 135: ...ation is shown in Fig 25 1 Reader to Card 100 ASK Modified Miller Coded Transfer speed 106 kbit s to 848 kbit s 2 Card to Reader Subcarrier Load Modulation Manchester Coded or BPSK transfer speed 106...

Page 136: ...framing according to ISO IEC 14443 A card response The internal CRC coprocessor calculates the CRC value based on the selected protocol In card mode for higher baud rates the parity is automatically i...

Page 137: ...PSK BPSK BPSK 12 2 3 FeliCa PCD mode The FeliCa mode is the general reader writer to card communication scheme according to the FeliCa specification The communication on a physical level is shown in F...

Page 138: ...per frame is limited to 28 All bytes in the buffer between the payload and the status byte are un initialized and therefore invalid FW has to take care that these bytes are not used The last word of...

Page 139: ...X_NUM_FRAMES_RECEIVED in the register RX_STATUS_REG is updated to indicate the number of received frames After the reception of the 8th frame which is the maximum supported a state change to next expe...

Page 140: ...tandard 12 3 NFC modes 12 3 1 NFCIP 1 modes 12 3 1 1 Overview The NFCIP 1 communication differentiates between an Active and a Passive Communication Mode Active Communication mode means both the initi...

Page 141: ...on direction 106 kbit s 212 kbit s 424 kbit s Initiator Target According to ISO IEC 14443A 100 ASK modified Miller Coded According to FeliCa Manchester Coded 8 30 ASK Target Initiator A dedicated host...

Page 142: ...l Note Transfer Speeds above 424 kbit s are not defined in the NFCIP 1 standard 12 3 1 4 ISO IEC14443 type A Card operation mode The PN7462 family can be addressed as a ISO IEC 14443 A card This means...

Page 143: ...it coding Manchester BPSK BPSK Bit encoding BPSK BPSK BPSK 12 3 1 6 NFCIP 1 framing and coding The NFCIP 1 framing and coding in Active and Passive Communication mode is defined in the NFCIP 1 standar...

Page 144: ...d Initiator Transmitter settings to automatically add the Sync Byte for transmission Adapted CRC preset value to correctly calculate the CRC 12 3 3 Card Mode Detection The PN7462 family provides the f...

Page 145: ...tection FW handling In case a protocol different to Type A Type B or Felica is detected FW needs to handle the complete activation process In such a case CMA is inactive and all IRQs are passed to FW...

Page 146: ...3 a Disable the AGC operation by writing 0 to CLIF_AGC_CONFIG0_REG AGC_MODE_ENABLE b Configure the AGC to manual mode by writing 0 to CLIF_AGC_CONFIG0_REG AGC_MODE_SEL c Configure the AGC input to ca...

Page 147: ...cks and reset used in the CLIF Table 184 summarized the input clocks of the CLIF module Table 184 Input clocks of CLIF Symbol Source Frequency Description clk_pll_27m12 PCR 27 12 MHz IP clock for acti...

Page 148: ...rated by the reader and the transmitted signal by the card ALM is kept to a minimum 12 4 3 CLIF Signal Processing SigPro Block This SigPro module performs digital signal processing The input is the de...

Page 149: ...bit generation calculation and appending of parity bits byte adjustments for bit oriented frames and encryption of the MIFARE products and on the other hand frame generation which covers creation of...

Page 150: ...ection ISO 14443B EOF detection Configurable stop conditions Frame check 12 4 6 Contactless Transceive module The Transceive module is handling the overall flow for contactless communication transmiss...

Page 151: ...field is present in card mode and other hand to avoid overlapping with an external field when the ICs driver shall be activated The external field indication includes masking a self generated RF Fiel...

Page 152: ...ith the CLIF clock and one additional timer T3 operating on HFO 20MHz or LFO 375 kHz RF Timers Timers T0 T1 and T2 have 20 bits and may be operated at clock frequencies derived from the 13 56MHz syste...

Page 153: ...R W 00000000h TxEncoder config register CLIF_TX_DATA_MOD_REG 0034h 32 R W 00000000h TXEncoder config register CLIF_TX_FRAME_CONFIG_REG 0038h 32 R W 00000200h TxEncoder config register INTERNAL_USE 003...

Page 154: ...SigPro register INTERNAL_USE 00C4h 32 R W 00000000h For internal use INTERNAL_USE 00C8h 32 R W 00000000h For internal use CLIF_AGC_CONFIG0_REG 00CCh 32 R W 00000000h AGC register INTERNAL_USE 00D0h 32...

Page 155: ...BLE_REG 3FDCh 32 W 00000000h Interrupt register CLIF_INT_STATUS_REG 3FE0h 32 R 00000000h Interrupt register CLIF_INT_ENABLE_REG 3FE4h 32 R 00000000h Interrupt register CLIF_INT_CLR_STATUS_REG 3FE8h 32...

Page 156: ...ess 0004h reset value Bit Symbol Access Value Description 31 3 RESERVED R 0 reserved 5 FORCE_TEMP_CLK_ ON_RFOFF R W 0 1 If set to 1 upon RFOFF event the clock is always switched to temporary clock no...

Page 157: ...signal indicating that a SOF has been detected 25 TX_RF_STATUS R 0 1 If set to 1 this bit indicates that the drivers are turned on meaning an RF Field is created by the device itself 24 RF_DET_STATUS...

Page 158: ...o trigger IRQ xxxx1x WaitTransmit state enabled to trigger IRQ xxx1xx Transmitting state enabled to trigger IRQ xx1xxx WaitReceive state enabled to trigger IRQ x1xxxx WaitForData state enabled to trig...

Page 159: ...et by HW a protocol is detected in automatic mode detection 7 0 TX_WAIT PRESCALER D 0 FFh Defines the prescaler reload value for the tx_wait timer Note This bit is set by HW a protocol is detected in...

Page 160: ...ternal RF field Note In case of an RFActiveError this bit is cleared by hardware 3 TX_COLL_AV_ENA BLE R W 0 1 Set to 1 enables automatic collision avoidance See ISO18092 for more details 2 TX_INITIAL_...

Page 161: ...ion 31 24 RESERVED R 0 Reserved 23 16 TX_DATA_MOD_WIDT H R W 0 FFh Specifies the length of a pulse for sending data with miller pulse modulation enabled The length is given by the number of carrier cl...

Page 162: ...eserved 15 13 TX_STOPBIT_TYPE R W 0 7 Enables the stop bit logic 1 and extra guard time logic 1 The value 0 disables transmission of stop bits 000b no stop bit no EGT 001b stop bit no EGT 010b stop bi...

Page 163: ...lue Description 31 28 RESERVED R 0 Reserved 27 0 TX_SYMBOL0_DEF R W 0 FFFFFFFh Pattern definition for Symbol0 Table 199 CLIF_TX_SYMBOL1_DEF_REG register address 0044h reset value Bit Symbol Access Val...

Page 164: ...ecifies the frequency of the subcarrier 0 424 kHz 1 848 kHz 2 0 TX_S01_BIT_FREQ R W 000 111 Specifies the frequency of the bit stream 000 1 695 MHz 001 Reserved for test 010 26 kHz 011 53 kHz 100 106...

Page 165: ...stream 000 1 695 MHz 001 3 39 MHz 010 26 kHz 011 53 kHz 100 106 kHz 101 212 kHz 110 424 kHz 111 848 kHz Table 203 CLIF_TX_OVERSHOOT_CONFIG_REG register address 0054h reset value Bit Symbol Access Val...

Page 166: ...new EMD options for PN7462 family are enabled 28 RX_PARITY_ERRO R_IS_EMD R W 0 1 If set to 1 a parity error in the 3rd 4th byte depending on RX_EMD_SUP setting is interpreted as an EMD error Otherwis...

Page 167: ...automatic mode detection is enabled and the corresponding communication is detected 00b Reception is stopped only if end of data communication is detected by the signal processing Note This value is s...

Page 168: ...ode if bit CollPosValid is set to 1 Note If RX_ALIGN is set to a value different to 0 this value is included in the RX_COLL_POS 23 RX_WRITE_ERROR R 0 1 This error flag is set to 1 if for an ongoing re...

Page 169: ...d Note This bit field is only valid when the RxMultiple is active bit RX_MULTIPLE_ENABLE set 8 0 RX_NUM_BYTES_R ECEIVED R 0 104h Indicates the number of bytes received The value is valid when the RxIR...

Page 170: ...reset value Bit Symbol Access Value Description 31 16 TX_CRC_PRESET_ VALUE R W 0 FFFFh Arbitrary preset value for the Tx Encoder CRC calculation 15 7 RESERVED R 0 Reserved 6 TX_CRC_BYTE2_E NABLE R W...

Page 171: ...gIn is detected 23 19 RESERVED R 0 Reserved 18 T0_START_ON_T3_ RUNNING R W 0 1 T0_START_EVENT If set the timer T0 is started when the timer T3 starts running 17 T0_START_ON_RX_ STARTED R W 0 1 T0_STAR...

Page 172: ...FIG_REG register address 007Ch reset value Bit Symbol Access Value Description 31 T1_STOP_ON_T3_E XPIRED R W 0 1 T1_STOP_EVENT If set the timer T1 is stopped when timer T3 raises its expiration flag 3...

Page 173: ...VENT If set the timer T1 is started when an internal RF field is turned on 10 T1_START_ON_RF_ OFF_INT R W 0 1 T1_START_EVENT If set the timer T1 is started when an internal RF field is turned off 9 T1...

Page 174: ...gIn is detected 23 19 RESERVED R 0 Reserved 18 T2_START_ON_T3_ RUNNING R W 0 1 T2_START_EVENT If set the timer T2 is started when the timer T3 starts running 17 T2_START_ON_RX_ STARTED R W 0 1 T2_STAR...

Page 175: ...the timer T2 will stop on expiration 0 After expiration the timer T2 will stop counting i e remain zero reset value 1 After expiration the timer T2 will reload its preset value and continue counting...

Page 176: ...ndicates that timer T1 is running busy 23 20 RESERVED R 0 Reserved 19 0 T1_VALUE R 00000h FFFFFh Value of 20 bit counter in timer T1 00h reset value Table 217 CLIF_TIMER2_OUTPUT_REG register address 0...

Page 177: ...during the SOF for an equal correlation value is done default activated 18 CORR_RESET_ON R W 0 1 The correlator is reset at a reset default activated 17 VALID_FILT_OFF R W 0 1 Disables a special filte...

Page 178: ...C_CONFIG0_REG register address 00CCh reset value Bit Symbol Access Value Description 31 INTERNAL_USE 1 R W 0 For internal use 30 24 FOR INTERAL USE 1 R W 0 7Fh For internal use 23 15 INTERNAL_USE 1 R...

Page 179: ...CLIF_AGC_CONFIG0_REG MODE_SEL 0 Note That in reset CLIF_AGC_CONFIG0_REG 0x00 and CLIF_AGC_INPUT_REG 0x00 and therefore the AGC output is AGC_CM_VALUE 0x00 0h Most sensitive largest Rx resistor i e non...

Page 180: ...R W 0 1 For internal use 1 0 INTERNAL_USE 1 R W 0 3h For internal use 1 Bit field are either set by HAL or use default value from CLIF EEPROM default settings Table 225 CLIF_RX_DATA_BUFFER_REG registe...

Page 181: ...detected is emulated 7 INTERNAL_USE 1 R W 0 1 For internal use 6 INTERNAL_USE 1 R W 0 1 For internal use 5 INTERNAL_USE 1 R W 0 1 For internal use 4 INTERNAL_USE 1 R W 0 1 For internal use 3 INTERNAL_...

Page 182: ...ccess Value Description 31 28 TX_GSN_CW_RM R W 0 Fh gsn settings continuous wave in reader mode 0000 lowest power level 1111 highest power level 27 24 INTERNAL_USE 1 R W 0 Fh For internal use 23 20 IN...

Page 183: ...R W 0 1 For internal use 15 INTERNAL_USE 1 R W 0 1 For internal use 14 INTERNAL_USE 1 R W 0 1 For internal use 13 INTERNAL_USE 1 R W 0 1 For internal use 12 INTERNAL_USE 1 R W 0 1 For internal use 11...

Page 184: ...ERNAL_USE 1 R W 0 1 For internal use 1 0 INTERNAL_USE 1 R W 0h 3h For internal use 1 Bit field are either set by HAL or use default value from CLIF EEPROM default settings Table 232 CLIF_ANA_AGC_REG r...

Page 185: ...r the residual carrier for the period the overshoot prevention pattern is active 23 18 RESERVED R 0 Reserved 17 TX _SET_BYPASS_SC_SHAPIN G R W 0 1 Bypasses switched capacitor shaping of the Transmitte...

Page 186: ...of the unmodulated carrier is defined relative to TVDD Used for 5 V driver input Table 236 CLIF_DPLL_INIT_REG register address 0208h reset value Bit Symbol Access Value Description 31 28 RESERVED R 0...

Page 187: ...D R 0 Reserved 1 0 RESERVED R W 0 3h Reserved 1 Bit field are either set by HAL or use default value from CLIF EEPROM default settings Table 237 CLIF_INT_CLR_ENABLE_REG register address 3FD8h reset va...

Page 188: ...use 13 INTERNAL_USE 1 W 0 1 For internal use 12 RF_ACTIVE_ERROR_IRQ_C LR_ENABLE W 0 1 Writing 1 to this register does clear the corresponding IRQ ENABLE flag 11 TX_RFON_IRQ_CLR_ENABL E W 0 1 Writing 1...

Page 189: ...Q ENABLE flag 21 RX_SOF_DET_IRQ_SET_EN ABLE W 0 1 Writing 1 to this register does set the corresponding IRQ ENABLE flag 20 RX_EMD_IRQ_SET_ENABLE W 0 1 Writing 1 to this register does set the correspon...

Page 190: ...alue Description 31 30 RESERVED R 0 Reserved 29 AGC_RFOFF_DET_ IRQ R 0 1 Set to 1 by hardware when the AGC has detected the external RF Field was switched off while transmitting in SL ALM mode Note On...

Page 191: ...hardware when the internally generated RF field was switched off 9 RFON_DET_IRQ R 0 1 Set to 1 by hardware when an external RF field is detected 8 RFOFF_DET_IRQ R 0 1 Set to 1 by hardware when an exte...

Page 192: ...R 0 1 If this bit is 1 the corresponding IRQ can propagate to the CPUs IRQ controller 17 TIMER1_IRQ_ENABLE R 0 1 If this bit is 1 the corresponding IRQ can propagate to the CPUs IRQ controller 16 TIME...

Page 193: ...ATUS R 0 1 Writing 1 to this register does clear the corresponding IRQ STATUS flag 25 TX_WATERLEVEL_IRQ_CLR _STATUS R 0 1 Writing 1 to this register does clear the corresponding IRQ STATUS flag 24 RX_...

Page 194: ...ding IRQ STATUS flag 1 TX_IRQ_CLR_STATUS R 0 1 Writing 1 to this register does clear the corresponding IRQ STATUS flag 0 RX_IRQ_CLR_STATUS R 0 1 Writing 1 to this register does clear the corresponding...

Page 195: ...ting 1 to this register does set the corresponding IRQ STATUS flag 11 TX_RFON_IRQ_SET_STATU S R 0 1 Writing 1 to this register does set the corresponding IRQ STATUS flag 10 TX_RFOFF_IRQ_SET_STATU S R...

Page 196: ...e transmitter current wave shaping settings can be controlled as well dependent on the selected protocol and the measured antenna load The PN7462 family allows to measure periodically the RX voltage T...

Page 197: ...ansmitter supply voltage configuration VDD TVDD 3 5 V 12 7 2 DPC EEPROM values Following table Table 243 shows the EEPROM address variable name as well as the description and access rights of all DPC...

Page 198: ...Size bit10 Duration Enable bit9 0 Duration DPC_THRSH_HI GH 0x201334 wAgcTrshHigh R W 30 Defines the AGC high threshold for each gear Number of gears can be 1 15 DPC_THRSH_L OW 0x20132C wAgcTrshLow R W...

Page 199: ...equal to 100us DPC_GUARD_S OF_DETECTED 0x201330 wGuardTimeSofDetec ted R W 2 Guard time after SoF or SC detection This is to avoid any DPC regulation between SoF SC and actual begin of reception Time...

Page 200: ...d in this document is subject to legal disclaimers NXP B V 2018 All rights reserved User manual COMPANY PUBLIC Rev 1 4 14 May 2018 314514 200 of 345 8 11 TAU_MOD_RISIN G Sign bit 3 bit value 12 15 RES...

Page 201: ...relative value change compared to actual setting of register CLIF_ANA_TX_SHAPE_CONTROL_REG for TX_SET_TAU_MOD_FALLING TX_SET_TAU_MOD_RISING and TX_RESIDUAL_CARRIER Table 244 PCD Shaping entry definit...

Page 202: ...claimers NXP B V 2018 All rights reserved User manual COMPANY PUBLIC Rev 1 4 14 May 2018 314514 202 of 345 subtracted from the existing configuration For an increasing gear value the defined change is...

Page 203: ...f the smart card Thermal and current limitation in the event of short circuit pins I O VCC Vcc regulation 5 V 3 V and 1 8 V Automatic activation and deactivation sequences initiated by software or by...

Page 204: ...chematics The following figure shows the basic application schematics to use the embedded contact smart card controller For more details on how to connect a smart card interface refer to the dedicated...

Page 205: ...Smart card power supply Must be decoupled through 2 capacitors GNDC 54 Ground pin for the smart card Must be connected to the smart card connector and to the main PCB ground plane RST 52 Reset pin for...

Page 206: ...its value CLK cycles when RST is LOW and up to MCH15 MCH0 bits value CLK cycles when RST is HIGH see the registers description The default value of MCL15 MCL0 MCH15 MCH0 bits is 42100d which gives a d...

Page 207: ...ve relates to a cold reset left part of Fig 37 If the card is mute has not answered the application may start a warm reset by setting WARM bit to logic level one see the registers description Then the...

Page 208: ...the card It will then flush the FIFO FIFO flush bit The next step consists in unlocking the transmission using dispe bit By writing this bit at logic level one and then at logic level zero if the fir...

Page 209: ...62 family is used to control several smart cards Fig 38 Contact interface architecture The external TDA is required to handle the smart card electrical interface The connection between the PN7462 fami...

Page 210: ...TDA8035 by changing the connection between the PN7462 family and the TDA8035 and by updating the FW to control the TDA8035 through GPIOs instead of the TDA8026 through I2C Here the SW modifications on...

Page 211: ...rly answer CounteR register ct_mcrl_lsb_reg 0028h 8 R W 00000074h Mute card CounteR RST Low register LSB ct_mcrl_msb_reg 002Ch 8 R W 000000A4h Mute card CounteR RST Low register MSB ct_mcrh_lsb_reg 00...

Page 212: ...spe disft MAN BGT AUTO CONV 0000 0000 ccr 2 R W RESERV ED RESERV ED SHL CST 5 SAN ACC2 ACC1 ACC0 XX00 0000 pcr R W C8 C4 RESERV ED RSTIN vccsel1 vccsel0 WARM START 11X0 0000 ecr R W EC7 EC6 EC5 EC4 EC...

Page 213: ...is only available for slot 1 this feature is ensured by CLKAUXen bit in ssr register for the auxiliary slot Another view of the registers can be obtained by looking to the functions they controlled W...

Page 214: ...US REGISTER UART RECEIVE REGISTER FIFO CONTROL REGISTER FIFO STATUS REGISTER UART TRANSMIT REGISTER PROGRAM DIVIDER REGISTERS 1 LSB MSB GUARD TIME REGISTER 1 UART CONFIGURATION REGISTER 11 POWER CONTR...

Page 215: ...nce is connected to PRESN pin for card detection When set to logic 1 an internal pull up resistance is connected to PRESN pin for card detection In conjunction with pres_con_no bit this enables to sup...

Page 216: ...00b Least significant byte of a 16 bit counter defining the ETU The ETU counter counts a number of cycles of the Contact Interface clock this defines the ETU The minimum acceptable value is 0001 0000b...

Page 217: ...1_reg The value 000 indicates that if only one parity error has occurred bit pe is set at logic 1 the value 111 indicates that bit pe will be set at logic 1 after 8 parity errors If a correct characte...

Page 218: ...t the first wrong received character 4 0 ftc 4 0 R W 0001b FIFO Threshold Configuration Define the number of received or transmitted characters in the FIFO triggering the ft bit in ct_usr1_reg The FIF...

Page 219: ...n used before transmitting the last character Note that when switching from to reception to from transmission mode the FIFO is flushed Any remaining bytes are lost 1 LCT R W 0b Last Character to Trans...

Page 220: ...ss read and write 6 FIFO flush R W 0b FIFO flush When set to logic 1 the FIFO is flushed whatever the mode reception or transmission is It can be used before any reception or transmission of character...

Page 221: ...hosen before enabling CLKAUX clock with CLKAUXen bit If bit SAN 1 then contact CLKAUX is the copy of the value of bit SHL 4 CST R W 0b Clock STop Slot 1 In the case of an asynchronous card bit CST def...

Page 222: ...defines the baudrate used by the Contact UART 13 6 2 9 Register ct_pcr_reg Power Control Register This configuration register enables to start or stop card sessions define the card supply voltage 5V 3...

Page 223: ...ounter used to check whether the card has answered too early Table 258 ct_ecr_reg address 0024h bit description Bit Symbol Access Reset Value Description 31 8 RESERVED 0 reserved 7 0 EC7 EC0 R W 1010...

Page 224: ...ster ct_mchr_msb_reg Mute card CounteR RST High register Most Significant Byte This configuration register is the most significant byte of a 16 bit counter used to check whether the card is mute when...

Page 225: ...rd When the controller wants to read a character from the card stored into the FIFO it reads it from this register in direct convention In case of byte access bit wrdacc 0 in register ct_ucr2_reg the...

Page 226: ...ngs CWT BWT Table 265 ct_tor1_reg address 004Ch bit description Bit Symbol Access Reset Value Description 31 8 RESERVED 0 reserved 7 0 TOL7 TOL0 W 0000 0000b Time Out Latched Programmable 8 bit ETU co...

Page 227: ...ansmission detected on pin I O after 65h is written in register ct_toc_reg When counter 1 reaches its terminal count an interrupt is given bit TO1 in register ct_usr2_reg is set and the counter automa...

Page 228: ...st start bit reception or transmission detected on pin I O after 77h is written in register ct_toc_reg When counter 1 reaches its terminal count an interrupt is given bit TO1 in register ct_usr2_reg i...

Page 229: ...before the next start bit This helps to verify that the card has not answered before 22 ETU after the last transmitted character or that the reader is not transmitting a character before 22 ETU after...

Page 230: ...ed in bits PEC 2 0 1 It is set at 10 5 ETU in the reception mode and at 11 5 ETU in the transmission mode A character received with a parity error is not stored into the FIFO and the card is supposed...

Page 231: ...logic 1 when the timer counter 3 has reached its terminal count Set to logic 0 after reading the byte 6 to2 R 0b Time Out counter2 Set to logic 1 when the timer counter 2 has reached its terminal coun...

Page 232: ...ces The I2C bus uses only two wires a serial clock line SCL and a serial data line SDA Each device is recognized by a unique address The I2C master controller is one of two I2C controllers supported b...

Page 233: ...s the slave address Next follows a number of data bytes The slave returns an acknowledge bit after each received byte Data transfer from a slave transmitter to a master receiver The first byte the sla...

Page 234: ...error during the ongoing communication the FIFO has to be cleared corresponding register to clear FIFO based on interrupt error When the FIFO is empty during the transmission the block will automatic...

Page 235: ...ual UM10858 All information provided in this document is subject to legal disclaimers NXP B V 2018 All rights reserved User manual COMPANY PUBLIC Rev 1 4 14 May 2018 314514 235 of 345 14 1 4 TX RX pro...

Page 236: ...family HW user manual UM10858 All information provided in this document is subject to legal disclaimers NXP B V 2018 All rights reserved User manual COMPANY PUBLIC Rev 1 4 14 May 2018 314514 236 of 34...

Page 237: ...bridge the undefined region of the falling edge of SCL in Standard and Fast modes This 300 ns hold time is computed based on the 27 12 MHz clock 27 12 MHz and written to the SDA_HOLD_REG register Tabl...

Page 238: ...r overview Table 275 I2CM Register overview base address 0x4003 0000 Name Address offset Width bits Access Reset value Description CONFIG_REG 1 0x0000 32 RW 0x00000000 Register fields to configure the...

Page 239: ...C 32 W 0x00000000 RX_DATA 0x0050 32 R 0x00000000 These register fields are used to read the received data from FIFO accessible as read only registers if I2C Master is configured for I2C Reception 0x00...

Page 240: ...ive of I2C Master Mode of operation 1 SLV_ADDRESSING R W 0x0 I2 C Slave 7 10 bit address selection 0 IP_MODE R W 0x0 I2 C Master Mode selection IP_MODE IP_MODE bit field determines the I2C master mode...

Page 241: ...78 SDA_HOLD_REG address offset 0x0008 Legend reset value mandatory value Bit Symbol Access Value Description 31 5 RESERVED R 0x0000000 reserved 4 0 SDA_HOLD R W 0x09 SDA Hold time For a detailed calcu...

Page 242: ...uals the I2C master internal FIFO 3 Byte granularity must be interpreted by the BYTECOUNT_CONFIG_REG 14 1 9 6 BYTECOUNT_CONFIG_REG This register s function is to configure the number of bytes to be tr...

Page 243: ..._MODE bit field of CONFIG_REG register 0 I2C_BUS_ACTIVE R 0x0 Indicates I2 C Transmission or Reception is On going I2C_BUS_ACTIVE The I2C_BUS_ACTIVE bit field is set when I2C transmission or reception...

Page 244: ...will be interpreted by the BYTECOUNT_CONFIG_REG register 3 The TX_DATA from offset address 0x0040 to 0x004C is order independent The TX data can be written to any of these offset address 0x0040 or 0x...

Page 245: ...Writing 1 to this register does clear the corresponding IRQ ENABLE flag 2 CLR_ENABLE_NACK W 0x0 Writing 1 to this register does clear the corresponding IRQ ENABLE flag 1 CLR_ENABLE_ARB_FAIL URE W 0x0...

Page 246: ...is on going 10 RX_FIFO_THRES R 0x0 Indicates that the FIFO threshold is reached while I2C reception is on going 9 FIFO_EMPTY R 0x0 Indicates that the FIFO empty condition is reached while I2C transmi...

Page 247: ...a collection of Clear Interrupt Status commands Writing 1 to this register does set the corresponding Interrupt Request ENABLE flag Writing 0 to this register has no effect Table 291 INT_CLR_STATUS_RE...

Page 248: ...e corresponding IRQ STATUS flag 7 4 RESERVED R 0x0 reserved 3 SET_STATUS_I2C_BUS_ ERROR W 0x0 Writing 1 to this register does set the corresponding IRQ STATUS flag 2 SET_STATUS_NACK W 0x0 Writing 1 to...

Page 249: ...E8 BYTE7 BYTE6 BYTE5 3 Third APB Write Transaction using write data XX XX XX BYTE9 Step 6 Enable the I2C Master transmission with an APB Write Transaction using write data 0x00000001 at offset address...

Page 250: ...e the byte count with an APB Write Transaction using write data 0x00000007 at offset address 0x00014 BYTECOUNT_CONFIG_REG Step 5 Enable the I2C Master reception with an APB Write Transaction using wri...

Page 251: ...SPI frame formats only SPI Block Guide V04 0114 Freescale specification Multiple data rates 1 1 51 2 09 2 47 3 01 4 52 5 42 and 6 78 Mbit s Up to two Slave Select with selectable polarity Programmable...

Page 252: ...ransfers serial data from the slave to the master and deals with different situation depending on whether the SPI is a slave a master or not selected by the Slave Select MOSI0 1 Master Out Slave in si...

Page 253: ...ig 51 SPI protocol with CPHA 0 NSS_PULSE 1 The SPI master automatically generates NSS signal Its polarity can be configured and it can be chosen to generate a pulse on NSS between each byte If more fl...

Page 254: ...valid buffer length Special attention should be paid to the fact that the RX buffer should not exceed the maximum address size RX_START_ADDR RX_LENGTH must be kept in System RAM address range The add...

Page 255: ...X TX buffer RX TX_CRC_PAYLOAD_OFFSET allows to define a number of bytes to be skipped from the CRC computation The initial value is 0xFF and the CRC is a xor of all data bytes CRC 0xFF xor Payload byt...

Page 256: ...ory last received byte and can check in CRC register that CRC_RX_VAL is 0 CRC xor CRC This is shown on figure Fig 56 Fig 56 RX CRC computation with RX_CRC_PAYLOAD_OFFSET 1 14 2 8 SPI Register overview...

Page 257: ...NT_SET_STATUS_REG 3FECh 32 W 00000000h Set interrupt 1 The reserved address 0x30 is mapped to a spare register 8 bits The value read from this location is 0x000000F0 Bits 7 4 are read write bits 3 0 a...

Page 258: ...Sampling of data occurs at odd edges 1 3 5 15 of the SCK clock 5 CPOL 1 R W 0 This bit selects an inverted or non inverted SPI clock To transmit data between SPI modules the SPI modules must have ide...

Page 259: ...RT W 0 1 Start RX Automatically returns to 0 14 2 9 4 SPIM_RX_BUFFER_REG This register is used to configure the RX buffer Table 298 SPIM_RX_BUFFER_REG address offset 0x000C Bit Symbol Access Reset Val...

Page 260: ...0 TX transfer of size 0 is allowed only if TX_APPEND_CRC is set TX_LENGTH 1 TX transfer payload of size 1 byte TX_LENGTH 2 TX transfer payload of size 2 byte TX_LENGTH 511 TX transfer payload of size...

Page 261: ...RESERVED R 0 Reserved 8 0 WATERLEVEL R W 0 Number of bytes received in incoming frame or sent in out coming frame before triggering an interrupt If set to 0 this feature is disabled 14 2 9 10 SPIM_BUF...

Page 262: ...RLEVEL_REACHED_ CLR_ENABLE W 0 1 clear enable for water level reached interrupt 0 no effect 1 EOT_CLR_ENABLE W 0 1 clear enable for EOT interrupt 0 no effect 0 EOR_CLR_ENABLE W 0 1 clear enable for EO...

Page 263: ...atus 0 EOR_STATUS R 0 EOR interrupt status 14 2 9 14 SPIM_INT_ENABLE_REG This register is a collection of Interrupt Enable commands Writing 1 to this register does set the corresponding Interrupt Requ...

Page 264: ...pt 0 no effect 0 EOR_CLR_STATUS W 0 1 clear EOR interrupt 0 no effect 14 2 9 16 SPIM_INT_SET_STATUS_REG This register is a collection of Set Interrupt Status commands Writing 1 to this register does s...

Page 265: ...4514 265 of 345 14 3 Host interfaces The Host interface block comprises four sub blocks shown in Fig 57 These are 1 I2C Slave 2 SPI Slave 3 HSU Slave 4 USB The host interface block selects the interfa...

Page 266: ...family can be also used as I2C slave interface This is the second of the two I2C controllers supported by PN7462 family For more details on the I2C master controller please refer to Section 14 1 The I...

Page 267: ...mode Hs mode Each mode is half duplex only The bitrate speeds for each mode are listed in the following table Table 313 I2C Mode Maximum Bitrates Mode Max Bitrate Standard mode Sm 100 kbit s Fast mod...

Page 268: ...s I2C I2C address matches the value stored in the Host IF TX buffer contains a frame Otherwise the Host Interface will return a NACK in response to the address phase 14 3 1 8 IDLE byte generation IDLE...

Page 269: ...em reset or an EOF is detected As a result the I2C reset output signal will be driven logic low Following the assertion of system reset HOSTIF_I2C_CONTROL_REG I2C_RESET_ENABLE is cleared to logic low...

Page 270: ...native mode 14 3 2 2 SPI Slave pin description Table 314 SPI pinning Pin Number Pin Name SPI slave Description 6 ATX_A NSS SPI active low Slave Select NSS 7 ATX_B MOSI SPI Master Output Slave Input MO...

Page 271: ...fields NCI_CRC_DISABLE and NCI_LENGTH_MODE both logic low in register HOSTIF_CONTROL_REG the same transport direction detector bytes are used e g if the first bit is logic low then it is a Host Write...

Page 272: ...port go is logic high RX buffer is available No frame overflow No buffer overflow Note that in Native mode frame overflow is not applicable 14 3 2 8 Response to SPI Host Read The Host Interface return...

Page 273: ...rt bit 8 data bits LSB Stop bit s Number of stop bits programmable for RX and TX 1 or 2 Configurable length of EOF 1 to 122 bits 14 3 3 2 HS UART pin description Table 315 HS UART pinning and signal a...

Page 274: ...bits The EOF is sampled at reception side before raising EOR interrupt and EOF is sent at the end of transmission before sending EOT interrupt This is shown in Fig 63 Fig 61 HSU byte transmission 14...

Page 275: ...U_TX_CLK_C ORRECT 9 6 2825 0 000_0000_0000 000_0000_0000 19 2 1412 0 000_0000_0000 001_0101_0101 38 4 706 0 000_0000_0000 010_0010_0010 57 6 470 0 000_0110_1001 001_1111_0111 115 2 235 0 000_0000_0011...

Page 276: ...imator was implemented The principle of this estimator is that the host sends a calibration byte of value 0x00 at beginning of each frame First transmission from the host interface to the host must oc...

Page 277: ...If the baud rate estimator overflows duration of first received 0x00 byte is too long then RX_FER interrupt will be raised and the value of HSU_EST_RX_DIVIDER_REG is set to 1023 14 3 3 8 RTS CTS flow...

Page 278: ...mpensate for the start bit detection and re synchronization which consumed 2 to 3 clock cycles not deterministic due to asynchronicity between RX and sampling clock Due to clock uncertainty given by s...

Page 279: ...rrupt does not stop receiving the frame 14 3 3 12 HS UART transmission from host interface to host The TX transmission should be performed in the following order Program HSU_RX_DIVIDER and HSU_TX_CLK_...

Page 280: ...nsferred is due to the fact that during the standby the host interface is inactive and may not be waken fast enough to sample the first bytes sent by the host In case the host communicates during the...

Page 281: ...n physical logical difference in protocols Table 320 ed format per interface Interface HDLL Native NCU NCI NCI NCI debug No Header No Header Header Header only No CRC CRC No CRC CRC I2C Yes Yes Yes Ye...

Page 282: ...e header is 2 bytes an offset of 3 is not permitted since this would result in the header being stored across the first two words in the buffer TX buffer There is no explicit disable field in register...

Page 283: ...G_REG RX n _HEADER_OFFSET The payload is stored from the second word onwards The CRC is extracted by the CRC checker for verification it is not stored in the RX buffer Frame transmission The buffer ma...

Page 284: ...1 1 No additional transport layer specified by NCI Number of received bytes stored in RX Length register Number of transmitted bytes stored in TX Length register NCI over I2C with CRC Y Y 0 1 0 0 Sup...

Page 285: ...CLR_DATA_READY_REG Receiving frames The Buffer Manager examines the Frame Length in the header and searches the next available buffer by checking that all the following conditions are true HOSTIF_BUFF...

Page 286: ...bit is only intended for debugging purposes 3 Setting HOSTIF_CLR_DATA_READY_REG CLR_RX_DATA_READY bit by the firmware will only cause HOSTIF_DATA_READY_STATUS_REG RX n _DATA_READY bit to be cleared i...

Page 287: ...in register HOSTIF_INT_STATUS_REG is set and bit HOSTIF_STATUS_REG TX_BUFFER_LOCK is cleared logic low 14 3 4 8 Waterlevel reached If the field WATERLEVEL in register HOSTIF_WATERLEVEL_REG is non zer...

Page 288: ...word in the buffer is reserved for storing the number of bytes received The output will remain high until the firmware sets RX_BUFFER_OVERFLOW_CLR_STATUS in register HOSTIF_INT_CLR_STATUS_REG An EOR...

Page 289: ...imeout Timer is reloaded with the value in HOSTIF_TIC_TIMEOUT_REG TX_TIMEOUT_VALUE after the transmission of each character Automatic start of timer after first character has been transmitted Automati...

Page 290: ...The EOR_STATUS flag in register HOSTIF_INT_STATUS_REG maintains logic low This feature is not applicable in native mode since none of the above error conditions can be detected 14 3 4 16 Sending fram...

Page 291: ...RNAL_USE 0030h 32 R W 00000000 For internal use INTERNAL_USE 0034h 32 R W 00000000 For internal use HOSTIF_BUFFER_RX0_CFG _REG 0038h 32 R W 08000000 Configuration of RX buffer 0 HOSTIF_BUFFER_RX1_CFG...

Page 292: ...Clear interrupt enable HOSTIF_INT_SET_ENABLE _REG 3FDCh 32 W 00000000 Set interrupt enable HOSTIF_INT_STATUS_REG 3FE0h 32 R 00000000 Interrupt status HOSTIF_INT_ENABLE_REG 3FE4h 32 R 00000000 Interru...

Page 293: ...load bytes in a short frame 0 2 bytes 1 3 bytes 1 STORE_RX_ERROR_ FRAMES R W 0 Store erroneous RX frames HOSTIF_DATA_READY_STATUS_REG RX n _DATA_READY is set by Host IF as if frame were received error...

Page 294: ...e I2C address HOSTIF_SPI_CONTROL_REG This register is used to control the SPI host interface Table 327 HOSTIF_SPI_CONTROL_REG address offset 0x0010 Bit Symbol Access Reset Value Description 31 2 RESER...

Page 295: ...OSTIF_HSU_SAMPLE_REG address offset 0x0018 Bit Symbol Access Reset Value Description 31 22 RESERVED R 0 Reserved 21 11 HSU_TX_CLK_CORR ECT R W 0 Used to correct clock division If TX_CLK_CORRECT i 1 th...

Page 296: ...s disabled 27 26 RX0_HEADER_OFFS ET 1 5 6 R W 0x02 Number of padding bytes to add before writing frame header to first word of RX buffer 0 Not applicable to Native Mode 25 RX0_SHORT_FRAME _BUFFER 1 2...

Page 297: ...address of RX buffer 1 Bits 1 0 are unused 1 Any change to this register is only taken into account if the buffer is not in use RX1_BUFFER_LOCK 0 However the register itself is updated 3 The frame len...

Page 298: ..._CFG_REG This register is used to configure the RX buffer 3 Table 335 HOSTIF_BUFFER_RX3_CFG_REG address offset 0x0044 Bit Symbol Access Reset Value Description 31 29 RESERVED R 0 Reserved 28 RX3_BUFFE...

Page 299: ...before sending to Host Not applicable to Native Mode 13 0 TX_START_ADDR 1 R W 0 Word start address of TX buffer Bits 1 0 are unused 1 Any change to this register is only taken into account if the buf...

Page 300: ...RX1 active when HOSTIF_CONTROL_REG NCI_LENGTH_M ODE 1 HOSTIF_BUFFER_RX2_LEN_REG This register is used to indicate the number of bytes stored in RX buffer 2 Table 338 HOSTIF_BUFFER_RX2_LEN_REG address...

Page 301: ...ROL_REG NCI_LENGTH_M ODE 1 HOSTIF_BUFFER_TX_LEN_REG This register is used to indicate the number of bytes stored in the TX buffer Table 340 HOSTIF_BUFFER_TX_LEN_REG address offset 0x005C Bit Symbol Ac...

Page 302: ...value Description 31 5 RESERVED R 0 Reserved 4 SET_TX_DATA_READ Y 1 W 0 Set TX_DATA_READY 3 SET_RX3_DATA_REA DY 2 W 0 Set RX3_DATA_READY 2 SET_RX2_DATA_REA DY 2 W 0 Set RX2_DATA_READY 1 SET_RX1_DATA_R...

Page 303: ...atus of data ready flags for buffers Table 345 HOSTIF_DATA_READY_STATUS_REG address offset 0x0070 Bit Symbol Access Reset Value Description 31 5 RESERVED R 0 Reserved 4 TX_DATA_READY 1 2 R 0 Frame val...

Page 304: ..._REG address offset 0x0078 Bit Symbol Access Reset Value Description 31 16 RESERVED R 0 Reserved 15 14 WR_PTR R 0 Pointer to next byte to write into RX_REG next byte inside word to write to memory 13...

Page 305: ...buffer 3 0000 no effect 16 CRC_NOK_CLR_ENA BLE W 0 1 clear enable for data link Layer CRC error interrupt 0 no effect 15 TX_TIMEOUT_CLR_E NABLE W 0 1 clear enable for inter character timeout TIC exce...

Page 306: ...nt itself is still triggered Thus even if the CPU is using a polling mechanism instead of being interrupt driven the firmware must still ensure that the event is cleared by setting the associated bit...

Page 307: ...E NABLE W 0 1 set enable for inter character timeout TIC exceeded on transmitted frame interrupt 0 no effect 14 11 RX_FRAME_OVERFL OW_SET_ENABLE W 0 0001 set enable for frame overflow interrupt for RX...

Page 308: ...to this register has no effect Table 350 HOSTIF_INT_STATUS_REG address offset 0x3FE0 Bit Symbol Access Reset Value Description 31 27 RESERVED W 0 Reserved 26 HSU_RX_FER_STATU S W 0 HSU RX frame error...

Page 309: ...t status for RX buffer 2 1000 Frame underflow interrupt status for RX buffer 3 6 TX_FRAME_NOT_AVAI LABLE_STATUS W 0 HOSTIF_DATA_READY_STATUS_REG T X_DATA_READY 0 when Host read request interrupt statu...

Page 310: ...ed interrupt enable for RX buffer 3 16 CRC_NOK_ENABLE W 0 Data link layer CRC error interrupt enable 15 TX_TIMEOUT_ENABL E W 0 Inter character timeout TIC exceeded on transmitted frame interrupt statu...

Page 311: ...S TATUS W 0 1 Clear HSU RX frame error interrupt status 0 no effect 25 BUFFER_CFG_CHAN GED_ERROR_CLR_S TATUS W 0 1 Clear buffer config changed during use interrupt status 0 no effect 24 AHB_WR_SLOW_CL...

Page 312: ...ar frame underflow interrupt for RX buffer 1 0100 clear frame underflow interrupt for RX buffer 2 1000 clear frame underflow interrupt for RX buffer 3 0000 no effect 6 TX_FRAME_NOT_AVAI LABLE_CLR_STAT...

Page 313: ...atus 0 no effect 21 WATERLEVEL_REAC HED_SET_STATUS W 0 1 set water level reached interrupt 0 no effect 20 17 RX_BUFFER_OVERF LOW_SET_STATUS W 0 0001 set max buffer size interrupt for RX buffer 0 0010...

Page 314: ...set EOR interrupt for RX buffer 3 0000 no effect 15 PN7462 family USB The Universal Serial Bus USB is a four wire bus that supports communication between a host and one or more up to 127 peripherals T...

Page 315: ...t transfers are used for periodic data transfer Bulk transfers are used when the latency of transfer is not critical Isochronous transfers have guaranteed delivery time but no error correction The USB...

Page 316: ...514 316 of 345 15 2 1 USB software interface Fig 68 USB software interface 15 3 Functional description 15 3 1 Endpoint command status list The picture below gives an overview on how the endpoint list...

Page 317: ...will do this when it receives a short packet or when the NBytes field transitions to zero or when firmware has written a one to the skip bit D R W Disabled 0 The selected endpoint is enabled 1 The sel...

Page 318: ...bulk or interrupt endpoint 1 Isochronous endpoint NBytes R W For OUT endpoints this is the number of bytes that can be received in this buffer For IN endpoints this is the number of bytes that must be...

Page 319: ...ument is subject to legal disclaimers NXP B V 2018 All rights reserved User manual COMPANY PUBLIC Rev 1 4 14 May 2018 314514 319 of 345 15 3 2 Control endpoint zero The flow charts in this section ind...

Page 320: ...ily HW user manual UM10858 All information provided in this document is subject to legal disclaimers NXP B V 2018 All rights reserved User manual COMPANY PUBLIC Rev 1 4 14 May 2018 314514 320 of 345 F...

Page 321: ...the corresponding USB EP Buffer Config bit to one The USB EP Buffer in use register indicates which buffer will be used by hardware when the next token is received When hardware clears the active bit...

Page 322: ...The USB protocol enforces power management by the USB device This becomes even more important if the device draws power from the bus bus powered device The following constraints should be met by the...

Page 323: ...zero 0x18 USB EP Buffer in use R W This bit is used for double buffering It indicates which buffer is in use for each endpoint 0x1C USB EP Buffer configuration register R W This bit indicates if the e...

Page 324: ...device this bit is set As long as this bit is set all received IN and OUT tokens will be NAKed by hardware SW must clear this bit by writing a one If this bit is zero hardware will handle the tokens t...

Page 325: ...re writes a zero to this bit the device will generate a remote wakeup Firmware can only write a zero to this bit when the LPM_REWP bit is set to 1 Hardware resets this bit when it receives a host init...

Page 326: ...t Symbol Value Description Reset Value Access 10 0 FRAME_NR Frame number It contains the frame number of the last successfully received SOF In case no SOF was received by the device at the beginning o...

Page 327: ...n be located Table 359 USB data buffer start address address offset 0x0C Reset value see configuration values Bit Symbol Description Reset Value Access 21 0 RESERVED Reserved RO 31 22 DA_BUF These are...

Page 328: ...E D Reserved 0 RO 15 4 2 7 USB Endpoint Buffer in use Table 362 USB Endpoint Buffer in use address offset 0x18 Reset value 0x00000000 Bit Symbol Value Description Reset Value Access 1 0 Reserved 0 RO...

Page 329: ...by writing a one to it 0 R W C 3 EP1IN Interrupt status register bit for the EP1 IN direction This bit will be set if the corresponding Active bit is cleared by hardware This is done in case the progr...

Page 330: ...ese bits the corresponding USB interrupt status bit is set When this register is read the same value as the USB interrupt status register is returned 0 R W 15 4 2 12 USB interrupt routing register Tab...

Page 331: ...int toggle address offset 0x34 Reset value 0x00000000 Bit Symbol Value Description Reset Value Access 29 0 TOGGLE Endpoint data toggle This field indicates the current value of the data toggle for the...

Page 332: ...ier DISC Disconnect in LLCP DM Disconnected Mode in LLCP EEPROM Electrically Erasable Programmable Read Only Memory FRI Forum reference implementation FRMR Frame Reject in LLCP GPIO General Purpose In...

Page 333: ...Layer PAX PArameter eXchange PCD Proximity Coupling Device PICC Proximity Integrated Circuit Card PDU Protocol Data Unit PTYPE PDU TYPE RNR Receive Not Ready RR Receive Ready RW Receive window size S...

Page 334: ...e the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in...

Page 335: ...mmunication diagram 139 Fig 31 Active communication mode 141 Fig 32 Passive communication mode 142 Fig 33 Contactless interface 147 Fig 34 Lookup tables for AGC value dependent dynamic configuration 1...

Page 336: ...vided in this document is subject to legal disclaimers NXP B V 2018 All rights reserved User manual COMPANY PUBLIC Rev 1 4 14 May 2018 314514 336 of 345 Fig 69 Endpoint command status list 317 Fig 70...

Page 337: ...EE_INT_SET_STATUS address offset 0x0FECh 27 Table 28 External interrupt sources 28 Table 29 NVIC register overview 30 Table 30 NVIC_IPRn bit assignments 30 Table 31 SWD pinning 31 Table 32 SysTick ti...

Page 338: ..._ATX_D_REG address offset 0x4C 95 Table 92 PCR_PADDWL_REQ_REG address offset 0x50 96 Table 93 PCR_PAD_INT_AUX_REG address offset 0x54 96 Table 94 PCR_PAD_IO_AUX_REG address offset 0x58 96 Table 95 PCR...

Page 339: ...ERS_TIMER1_CONTROL_REG address offset 0x000C 129 Table 154 TIMERS_TIMER1_TIMEOUT_REG address offset 0x0010 130 Table 155 TIMERS_TIMER1_COUNT_REG address offset 0x0014 130 Table 156 TIMERS_TIMER2_CONTR...

Page 340: ...ddress 0058h 165 Table 205 CLIF_RX_CONFIG_REG register address 005Ch 166 Table 206 CLIF_RX_STATUS_REG register address 0060h 168 Table 207 CLIF_CRC_RX_ CONFIG_REG register address 006Ch 169 Table 208...

Page 341: ...ress 002Ch bit description 223 Table 261 ct_mchr_lsb_reg address 0030h bit description 224 Table 262 ct_mchr_msb_reg address 0034h bit description 224 Table 263 ct_ssr_reg address 0038h bit descriptio...

Page 342: ...90 Table 323 HOSTIF_STATUS_REG address offset 0x0000 292 Table 324 HOSTIF_CONTROL_REG address offset 0x0004 293 Table 325 HOSTIF_HEADER_CONTROL_REG address offset 0x0008 293 Table 326 HOSTIF_I2C_CONTR...

Page 343: ...6 Table 358 USB EP command status list address address offset 0x08 327 Table 359 USB data buffer start address address offset 0x0C 327 Table 360 Link Power Management register address offset 0x10 327...

Page 344: ...57 7 3 CLIF PLL 60 7 4 Register overview and description 61 7 5 Clock Status Register description 62 7 6 USB PLL register description 64 7 7 CLIF PLL register description 67 8 Power clock and reset P...

Page 345: ...ddresses please send an email to salesaddresses nxp com Date of release 14 May 2018 314514 Document identifier UM10858 14 2 SPI Master Interface 251 14 3 Host interfaces 265 15 PN7462 family USB 314 1...

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