NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
User manual
COMPANY PUBLIC
Rev. 1.4 — 14 May 2018
314514
81 of 345
PAD Name
Power Supply
MISO_M, MOSI_M, SCLK_M, NSS_M
PVDD_IN_M
SCL_M, SDA_M
PVDD_IN_M
GPIO1 to GPIO12
PVDD_IN
SWDIO, SWDCLK
PVDD_IN
IRQ
PVDD_IN
8.6.1 Hard Power Down (HPD) State of Pads
In the Hard Power Down mode, all digital pad signals will be masked.
8.6.2 Pad state in absence of PVDD
In absence of PVDD all input and output drivers will be disabled with a gate and all input
signals from the PAD will be clamped.
8.6.3 Selecting host interface
The PN7462 family connects to host through four pads: ATX_A/ATX_B/ATX_C/ATX_D.
There are three protocols by which PN7462 family connects to host through pads:
I2C/high-speed-UART/SPI. The selection of which protocol to connect with is done by
using configuration of PCR_SYS_REG.hif_selection bits in PCR_SYS_REG register
described in
8.7 Register overview
Table 71. Register overview (base address 0x4002 4000)
Name
Address
Offset
Width
(bits)
Access
Reset value
Description
PCR_GPREG0_REG
0x0000
32
rw-
0x00000000
General-purpose register 0 for SW
PCR_GPREG1_REG
0x0004
32
rw-
0x00000000
General-purpose register 1 for SW
PCR_GPREG2_REG
0x0008
32
rw-
0x00000000
General-purpose register 2 for SW
PCR_SYS_REG
0x000c
32
rw-
0x00000100
system configuration like Hostif selection
and CT enabling
PCR_PMU_REG
0x0010
32
rw-
0x0217010C
PMU interface. For LDO, bandgap,
DC-to-DC converter configuration and
sequences
PCR_RFLD_REG
0x0014
32
rw-
0x00004032
CLIF configuration
PCR_TEMP_REG
0x0018
32
rw-
0x00058888
temperature sensor calibration
information
PCR_HOSTIF_WAKEUP_CF
G_REG
0x001c
32
rw-
0x00000000
configuring wake-up source for standby
and Suspend
PCR_WAKEUP_CFG_REG
0x0020
32
rw-
0x00000000
configuring wake-up source for standby
and Suspend
PCR_GPIO_WAKEUP_CFG_
REG
0x0024
32
rw-
0x000000FF
configuring wake-up source for standby
and suspend
