NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858
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© NXP B.V. 2018. All rights reserved.
User manual
COMPANY PUBLIC
Rev. 1.4 — 14 May 2018
314514
273 of 345
End of Frame:
Signal
EOF
is generated on the rising edge of SPI Slave Select
since a
Host must write the frame in a single write access.
14.3.2.10 Pads and pad control
The SPI interface signals are routed to the pads via the PCR.
14.3.3 High speed UART
The High Speed Asynchronous Receiver/Transmitter (HS UART) is another host
interface supported by PN7462 family. The HSUART is designed to support bit rates up
to 1.288 Mbit/s. The HSUART can operate only in slave mode.
14.3.3.1 HS UART features
•
Standard bit-rates - 9600, 19200, 38400, 57600, 115200, and faster speed rate up to
1.288 Mbit/s
•
Full Duplex supported
•
Supports only one operational mode: Start bit, 8 data bits (LSB), Stop bit(s)
•
Number of “stop bits” programmable for RX and TX (1 or 2)
•
Configurable length of EOF (1 to 122 bits)
14.3.3.2 HS UART pin description
Table 315. HS UART pinning and signal assignments
Pin Number
Pin Name
HSU
Description
6
ATX_A
HSUART RX
High Speed UART - Reception Line
7
ATX_B
HSUART TX
High Speed UART - Transmission Line
8
ATX_C
HSUART RTS
High Speed UART – Host interface is ready to
receive
9
ATX_D
HSUART CTS
High Speed UART - Host is ready to receive
14.3.3.3 HS UART transmission
This interface comprises four wires connected to pads via the PCR:
•
Transmit Data (HSU_TX)
•
Receive Data (HSU_RX)
•
Clear to Send (HSU_CTS_n)
•
Request to Send (HSU_RTS_n)
The HS UART takes bytes of data and transmits the individual bits in a sequential
fashion. At the destination, a second UART re-assembles the bits into complete bytes.
The term “Asynchronous” means no clock being transferred over the line (both the
transmitter and the receiver know the baud rate before transmission). The frame is made
of several independent bytes. In the receive mode the HS UART works as a slave, while
