NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858
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© NXP B.V. 2018. All rights reserved.
User manual
COMPANY PUBLIC
Rev. 1.4 — 14 May 2018
314514
28 of 345
Bit
Symbol
Access
Value
Description
0
ee_prog_dat_completed_int_SE
T_STATUS
W
0
EEPROM programming completed
interrupt set status command
4. Nested Vectored Interrupt Controller (NVIC)
The NVIC is an integral part of the Cortex-M0. The tight coupling to the CPU allows for a
low interrupt latency and efficient processing of late arriving interrupts. The NVIC controls
system exceptions and peripheral interrupts. Its control registers are accessible as
memory-mapped devices.
4.1 NVIC features
•
Controls system exceptions and peripheral interrupts
•
Supports 32 vectored interrupts
•
Four interrupt priority levels, with hardware priority level masking
•
Non-mask able interrupt (NMI) connected to the watchdog interrupt.
•
Software interrupt generation
4.2 Interrupt sources
The following table lists the interrupt sources available in the PN7462 family
microcontroller
Table 28. External interrupt sources
EIRQ# Source
Description
0
Timer 0/1/2/3
general-purpose timer 0/1/2/3 interrupt
1
-
Reserved
2
CLIF
contactless interface module interrupt
3
EECTRL
EEPROM controller
4
-
Reserved
5
-
Reserved
6
Host IF
TX or RX buffer from I2C, SPI, HSU, or USB module
7
Contact IF
ISO7816 contact module interrupt
8
-
Reserved
9
PMU/
TXLDO
power management unit (temperature sensor, TXLDO
overcurrent detection, overload, VBUS level)
10
SPIMaster
TX or RX buffer from SPI master module
11
I2CMaster
TX or RX buffer from I2C master module
12
PCR
high temperature from temperature sensor 0 and 1,
interrupt to CPU from PCR to indicate wakeup from suspend
mode, out of standby, out of suspend, event on GPIO’s
configured as inputs.
13
PCR
interrupt common GPIO 1 to 12
