NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858
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© NXP B.V. 2018. All rights reserved.
User manual
COMPANY PUBLIC
Rev. 1.4 — 14 May 2018
314514
280 of 345
The TX_DIVIDER will be programmed to 0 (RX_DIVIDER value is used), and a provided
script will be used to compute TX_CORRECT.
14.3.3.13
Data generation
The data generation is a bit easier than data sampling, since there is no need to compute
when the middle of a bit happens. Also there is nothing to resynchronize. The output data
will be in sync with the sample clock. The TX generator is a simple clock counter, using
HSU_DIVIDER registers and HSU_TX_CORRECT for each bit to send. For TX,
HSU_DIVIDER = HSU_RX_D HSU_TX_DIVIDER, with TX_DIVIDER=0 or 1
only. This is due to the fact that for optimization, the RX_divider is sometimes decreased
by 1 to finely tune when sampling happens. At the end of each period, next bit is sent
over HSU_TX.
14.3.3.14
HS UART and HDLL mode
In HDLL mode, the host is expected to send HDLL frames starting with the 2 bytes HDLL
header, followed by payload then 2 bytes CRC) with NO extra bytes. All data except
CRC will be stored in the memory. No difference to I2C/SPI is expected.
14.3.3.15
HS UART and NCI mode
In NCI mode, the host may start each frame with 1 to 3 dummy bytes. This dummy byte
will be always stored in the memory. The reason why these dummy bytes are transferred
is due to the fact that during the standby, the host interface is inactive and may not be
waken fast enough to sample the first bytes sent by the host. In case the host
communicates during the standby, the PCR will raise the RTS to 1 to prevent the host
from sending other data, and we assume that no more than 3 bytes will be sent. These 3
bytes will be lost. The host cannot determine, when PN7462 family is in the standby.
Therefore, we recommend sending always 3 dummy bytes at beginning of frames in the
NCI mode.
14.3.3.16
Wake-up from standby
In NCI mode, it is expected that up to dummy 3 bytes are lost when the host wakes-up
the PN7462 family from the standby. Reception of these bytes can be simulated in order
to ease writing of the firmware. For this reason, there is a control bit (WAKEUP_STANDY
in HSU_CONTROL_REG) which can be used only once. When this bit is set, the
HSUART will simulate reception of 1 to 3 dummy bytes (number configured by
WAKEUP_BYTES) at first address of reception buffer. Next frames will be stored in
memory without any byte addition.
In HDLL mode, WAKEUP_STANDY should not be programmed. The message sent by
the host to wake-up the PN7462 family can be a simple byte which will be discarded by
PCR and not seen by the host interface.
14.3.3.17
Pads and pad control
The UART interface signals are routed to the pads via the PCR.
14.3.4 Buffer Manager
The buffer manager transfers data between the host interface and the SRAM. It is shared
between High-Speed UART, I2C and SPI interfaces whereas USB has its own buffer
management. It processes the incoming frames (extracts the packet length, verifies the
