65
8331B–AVR–03/12
Atmel AVR XMEGA AU
5.14.4
TRIGSRC – Trigger Source
• Bit 7:0 – TRIGSRC[7:0]: Channel Trigger Source Select
These bits select which trigger source is used for triggering a transfer on the DMA channel. A
zero value means that the trigger source is disabled. For each trigger source, the value to put in
the TRIGSRC register is the sum of the module’s or peripheral’s base value and the offset value
for the trigger source in the module or peripheral.
shows the base value for
all modules and peripherals.
shows the offset
value for the trigger sources in the different modules and peripheral types. For modules or
peripherals which do not exist for a device, the transfer trigger does not exist. Refer to the device
datasheet for the list of peripherals available.
If the interrupt flag related to the trigger source is cleared or the interrupt level enabled so that an
interrupt is triggered, the DMA request will be lost. Since a DMA request can clear the interrupt
flag, interrupts can be lost.
Note:
For most trigger sources, the request is cleared by accessing a register belonging to the periph-
eral with the request. Refer to the different peripheral chapters for how requests are generated
and cleared.
Table 5-8.
DMA channel destination address mode settings.
DESTDIR[1:0]
Group Configuration
Description
00
FIXED
Fixed
01
INC
Increment
10
DEC
Decrement
11
-
Reserved
Bit
7
6
5
4
3
2
1
0
TRIGSRC[7:0]
TRIGSRC
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Table 5-9.
DMA trigger source base values for all modules and peripherals.
TRIGSRC Base Value
Group Configuration
Description
0x00
OFF
Software triggers only
0x01
SYS
Event system DMA triggers base value
0x04
AES
AES DMA trigger value
0x10
ADCA
ADCA DMA triggers base value
0x15
DACA
DACA DMA trigger bas
0x20
ADCB
ADCB DMA triggers base value
0x25
DACB
DACB DMA triggers base value
0x40
TCC0
Timer/counter C0 DMA triggers base value
0x46
TCC1
Timer/counter C1 triggers base value