263
8331B–AVR–03/12
Atmel AVR XMEGA AU
21.3
General TWI Bus Concepts
The TWI provides a simple, bidirectional, two-wire communication bus consisting of a serial
clock line (SCL) and a serial data line (SDA). The two lines are open-collector lines (wired-AND),
and pull-up resistors (Rp) are the only external components needed to drive the bus. The pull-up
resistors provide a high level on the lines when none of the connected devices are driving the
bus
The TWI bus is a simple and efficient method of interconnecting multiple devices on a serial bus.
A device connected to the bus can be a master or slave, where the master controls the bus and
all communication.
illustrates the TWI bus topology.
Figure 21-1.
TWI bus topology.
A unique address is assigned to all slave devices connected to the bus, and the master will use
this to address a slave and initiate a data transaction.
Several masters can be connected to the same bus, called a multi-master environment. An arbi-
tration mechanism is provided for resolving bus ownership among masters, since only one
master device may own the bus at any given time.
A device can contain both master and slave logic, and can emulate multiple slave devices by
responding to more than one address.
A master indicates the start of a transaction by issuing a START condition (S) on the bus. An
address packet with a slave address (ADDRESS) and an indication whether the master wishes
to read or write data (R/W) are then sent. After all data packets (DATA) are transferred, the mas-
ter issues a STOP condition (P) on the bus to end the transaction. The receiver must
acknowledge (A) or not-acknowledge (A) each byte received.
TWI
DEVICE #1
R
P
R
P
R
S
R
S
SDA
SCL
V
CC
TWI
DEVICE #2
R
S
R
S
TWI
DEVICE #N
R
S
R
S
Note: R
S
is optional
