261
8331B–AVR–03/12
Atmel AVR XMEGA AU
20.16 Register Summary – USB Module
20.17 Register Summary – USB Endpoint
The address to the first configuration byte is (EPPTR[15:0] + 16 × endpoint address) for OUT
endpoints and (EPPTR[15:0] + 16 × endpoint a 8) for IN endpoints.
20.18 Register Summary – Frame
The address to the frame configuration byte is (MAXEP + 1) << 4. For instance with MAXEP = 3,
the first address would be located at offset address 0x40.
20.19 USB Interrupt Vector Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
+0x00
CTRLA
ENABLE
SPEED
FIFOEN
STFRNUM
MAXEP[3:0]
+0x01
CTRLB
–
–
–
PULLRST
–
RWAKEUP
GNACK
ATTACH
+0x02
STATUS
–
–
–
–
UPRESUME
RESUME
SUSPEND
BUSRST
+0x03
ADDR
–
ADDR[6:0]
+0x04
FIFOWP
–
–
–
FIFOWP[4:0]
+0x05
FIFORP
–
–
–
FIFORP[4:0]
+0x06
EPPTRL
EPPTR[7:0]
+0x07
EPPTRH
EPPTR[15:8]
+0x08
INTCTRLA
SOFIE
BUSEVIE
BUSERRIE
STALLIE
–
–
INTLVL[1:0]
+0x09
INTCTRLB
–
–
–
–
–
–
TRNIE
SETUPIE
+0x0A
INFLAGSACLR
SOFIF
SUSPENDIF
RESUMEIF
RSTIF
CRCIF
UNFIF
OVFIF
STALLIF
+0x0B
INFLAGSASET
SOFIF
SUSPENDIF
RESUMEIF
RSTIF
CRCIF
UNFIF
OVFIF
STALLIF
+0x0C
INFLAGSBCLR
–
–
–
–
–
–
TRNIF
SETUPIF
+0x0D
INFLAGSBSET
–
–
–
–
–
–
TRNIF
SETUPIF
+0x0E
Reserved
–
–
–
–
–
–
–
–
+0x0F
Reserved
–
–
–
–
–
–
–
–
+0x10-0X39
Reserved
–
–
–
–
–
–
–
–
+0x3A
CALL
CAL[7:0]
+0x3B
CALH
CAL[15:8]
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
+0x00
STATUS
STALL
OVF/UNF
TRNCOMPL0
SETUP
BANK
BUSNACK1
BUSNACK0
TOGGLE
CRC
TRNCOMPL1
Isochromous
+0x01
CTRL
TYPE[1:0]
MULTIPKT
PINGPONG
INTDSBL
STALL
BUFSIZE[1:0]
BUFSIZE[2:0]
Isochromous
+0x02
CNTL
CNT[7:0]
+0x03
CNTH
AZLP
–
–
–
–
–
CNT[9:8]
+0x04
DATAPTRL
DATAPTR[7:0] 258
DATAPTRH
DATAPTR[15:8] 258
+0x06
AUXDATAL
AUXDATA[7:0] 259
+0x07
AUXDATAH
AUXDATA[15:8] 259
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
+0x00
FRAMENUML
FRAMENUM[7:0]
+0x01
FRAMENUMH
FRAMEERR
–
–
–
–
FRAMENUM[10:8]
Table 20-6.
USB interrupt vectors and their word offset addresses.
Offset
Source
Interrupt Description
0x00
BUSEVENT_vect
SOF, suspend, resume, bus reset, CRC, underflow, overflow, and stall error interrupts
0x02
TRNCOMPL_vect
Transaction complete interrupt