301
8331B–AVR–03/12
Atmel AVR XMEGA AU
23.7.3
Parity Checker
When enabled, the parity checker calculates the parity of the data bits in incoming frames and
compares the result with the parity bit of the corresponding frame. If a parity error is detected,
the parity error flag is set.
23.7.4
Disabling the Receiver
A disabling of the receiver will be immediate. The receiver buffer will be flushed, and data from
ongoing receptions will be lost.
23.7.5
Flushing the Receive Buffer
If the receive buffer has to be flushed during normal operation, read the DATA location until the
receive complete interrupt flag is cleared.
23.8
Asynchronous Data Reception
The USART includes a clock recovery and a data recovery unit for handling asynchronous data
reception. The clock recovery unit is used for synchronizing the incoming asynchronous serial
frames at the RxD pin to the internally generated baud rate clock. It samples and low-pass filters
each incoming bit, thereby improving the noise immunity of the receiver. The asynchronous
reception operational range depends on the accuracy of the internal baud rate clock, the rate of
the incoming frames, and the frame size in number of bits.
23.8.1
Asynchronous Clock Recovery
The clock recovery unit synchronizes the internal clock to the incoming serial frames.
illustrates the sampling process for the start bit of an incoming frame. The sample
rate is 16 times the baud rate for normal mode, and eight times the baud rate for double speed
mode. The horizontal arrows illustrate the synchronization variation due to the sampling pro-
cess. Note the larger time variation when using the double speed mode of operation. Samples
denoted as zero are samples done when the RxD line is idle; i.e., when there is no communica-
tion activity.
Figure 23-6.
Start bit sampling.
When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the
start bit detection sequence is initiated. Sample 1 denotes the first zero-sample, as shown in the
figure. The clock recovery logic then uses samples 8, 9, and 10 for normal mode and samples 4,
5, and 6 for double speed mode to decide if a valid start bit is received. If two or three samples
have a low level, the start bit is accepted. The clock recovery unit is synchronized, and the data
recovery can begin. If two or three samples have a high level, the start bit is rejected as a noise
spike, and the receiver looks for the next high-to-low transition. The process is repeated for each
start bit.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
START
IDLE
0
0
BIT 0
3
1
2
3
4
5
6
7
8
1
2
0
RxD
Sample
(U2X = 0)
Sample
(U2X = 1)
