265
8331B–AVR–03/12
Atmel AVR XMEGA AU
21.3.3
Bit Transfer
As illustrated by
, a bit transferred on the SDA line must be stable for the entire high
period of the SCL line. Consequently the SDA value can only be changed during the low period
of the clock. This is ensured in hardware by the TWI module.
Figure 21-4.
Data validity.
Combining bit transfers results in the formation of address and data packets. These packets
consist of eight data bits (one byte) with the most-significant bit transferred first, plus a single-bit
not-acknowledge (NACK) or acknowledge (ACK) response. The addressed device signals ACK
by pulling the SCL line low during the ninth clock cycle, and signals NACK by leaving the line
SCL high.
21.3.4
Address Packet
After the START condition, a 7-bit address followed by a read/write (R/W) bit is sent. This is
always transmitted by the master. A slave recognizing its address will ACK the address by pull-
ing the data line low for the next SCL cycle, while all other slaves should keep the TWI lines
released and wait for the next START and address. The address, R/W bit, and acknowledge bit
combined is the address packet. Only one address packet for each START condition is allowed,
also when 10-bit addressing is used.
The R/W bit specifies the direction of the transaction. If the R/W bit is low, it indicates a master
write transaction, and the master will transmit its data after the slave has acknowledged its
address. If the R/W bit is high, it indicates a master read transaction, and the slave will transmit
its data after acknowledging its address.
21.3.5
Data Packet
An address packet is followed by one or more data packets. All data packets are nine bits long,
consisting of one data byte and an acknowledge bit. The direction bit in the previous address
packet determines the direction in which the data are transferred.
21.3.6
Transaction
A transaction is the complete transfer from a START to a STOP condition, including any
repeated START conditions in between. The TWI standard defines three fundamental transac-
tion modes: Master write, master read, and a combined transaction.
illustrates the master write transaction. The master initiates the trans-
action by issuing a START condition (S) followed by an address packet with the direction bit set
to zero (W).
SDA
SCL
DATA
Valid
Change
Allowed
