195
8331B–AVR–03/12
Atmel AVR XMEGA AU
Figure 15-2.
Clock selection.
The peripheral clock (clk
PER
) is fed into the common prescaler (common for all timer/counters in
a device). A selection of prescaler outputs from 1 to 1/1024 is directly available. In addition, the
whole range of time prescalings from 1 to 2
15
is available through the event system.
The clock selection (CLKSEL) selects one of the clock prescaler outputs or an event channel for
the high-byte counter (HCNT) and low-byte counter (LCNT). By using the event system, any
event source, such as an external clock signal, on any I/O pin can be used as the clock input.
By default, no clock input is selected, and the counters are not running.
15.5
Counter Operation
The counters will always count in single-slope mode. Each counter counts down for each clock
cycle until it reaches BOTTOM, and then reloads the counter with the period register value at the
following clock cycle.
Figure 15-3.
Counter operation.
, the counter can change the counter value while running. The write
access has higher priority than the count clear, and reloads and will be immediate.
15.5.1
Changing the Period
The counter period is changed by writing a new TOP value to the period register. Since the
counter is counting down, the period register can be written at any time without affecting the cur-
rent period, as shown in
. This prevents wraparound and generation of
odd waveforms.
clk
PER
/
2
{0,...,15}
CLKSEL
CNT
clk
PER
/
{1,2,4,8,64,256,1024}
Common
Prescaler
clk
PER
event channels
Event
System
events
CNT
BOTTOM
MAX
"reload"
TOP
CNT written
