412
8331B–AVR–03/12
Atmel AVR XMEGA AU
The active states are:
• Capture DR: Parallel data from the PDI are sampled into the PDICOM data register
• Shift DR: The PDICOM data register is shifted by the TCK input
• Update DR: Commands or operands are parallel-latched from the PDICOM data register into
the PDI
31.5
Boundary Scan Chain
The boundary scan chain has the capability of driving and observing the logic levels on the I/O
pins. To ensure a predictable device behavior during and after the EXTEST, CLAMP, and
HIGHZ instructions, the device is automatically put in reset. During active reset, the external
oscillators, analog modules, and non-default port pin settings (like pull-up/down, bus-keeper,
wired-AND/OR) are disabled. It should be noted that the current device and port pin state are
unaffected by the SAMPLE and PRELOAD instructions.
31.5.1
Scanning the Port Pins
shows the boundary scan cell used for all the bidirectional port pins.
This cell is able to control and observe both pin direction and pin value via a two-stage shift reg-
ister. When no alternate port function is present, output control corresponds to the DIR register
value, output data corresponds to the OUT register value, and input data corresponds to the IN
register value (tapped before the input inverter and input synchronizer). Mode represents either
an active CLAMP or EXTEST instruction, while shift DR is set when the TAP controller is in its
shift DR state.
Figure 31-2.
Boundary scan cell for bi-directional port pin.
D
Q
D Q
D Q
D
Q
Input Data
(IN)
Output Data
(IN)
Output Control
(DIR)
Mode
Pn
Shift DR
To next cell
From last cell
Clock DR
Update DR
0
1
0
1
0
0
1
1
En
