290
8331B–AVR–03/12
Atmel AVR XMEGA AU
22.7
Register Description
22.7.1
CTRL – Control register
• Bit 7 – CLK2X: Clock Double
When this bit is set, the SPI speed (SCK frequency) will be doubled in master mode (see
).
• Bit 6 – ENABLE: Enable
Setting this bit enables the SPI module. This bit must be set to enable any SPI operations.
• Bit 5 – DORD: Data Order
DORD decides the data order when a byte is shifted out from the DATA register. When DORD is
written to one, the least-significant bit (lsb) of the data byte is transmitted first, and when DORD
is written to zero, the most-significant bit (msb) of the data byte is transmitted first.
• Bit 4 – MASTER: Master Select
This bit selects master mode when written to one, and slave mode when written to zero. If SS is
configured as an input and driven low while master mode is set, master mode will be cleared.
• Bit 3:2 – MODE[1:0]: Transfer Mode
These bits select the transfer mode. The four combinations of SCK phase and polarity with
respect to the serial data are shown in
. These bits decide whether the
first edge of a clock cycle (leading edge) is rising or falling, and whether data setup and sample
occur on the leading or trailing edge.
When the leading edge is rising, the SCK signal is low when idle, and when the leading edge is
falling, the SCK signal is high when idle.
• Bits 1:0 – PRESCALER[1:0]: Clock Prescaler
These two bits control the SPI clock rate configured in master mode. These bits have no effect in
slave mode. The relationship between SCK and the peripheral clock frequency ( clk
PER
) is
shown in
Bit
7
6
5
4
3
2
1
0
CLK2X
ENABLE
DORD
MASTER
MODE[1:0]
PRESCALER[1:0]
CTRL
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Table 22-2.
SPI transfer modes.
MODE[1:0]
Group Configuration
Leading Edge
Trailing Edge
00
0
Rising, sample
Falling, setup
01
1
Rising, setup
Falling, sample
10
2
Falling, sample
Rising, setup
11
3
Falling, setup
Rising, sample
