483
8331B–AVR–03/12
Atmel AVR XMEGA AU
36.13 SDRAM 8-bit read
Figure 36-40.
Single read
Precha
rge All Ba
nks
Bank Adr
0x0
D[7:0]
Row Adr
Col Adr
0x400
Ac
tive
Re
ad
NO
P
*
NO
P
***
*
Single read
Da
ta s
ampl
ed
NO
P
**
Cl
ock
su
sp
end*
**
** NOP is only inserted for CAS3
**** The number of NOPs is equal to WRDLY[1:0] + 1 (WRDLY = 0 is shown)
***** The number of NOPs is equal to RPDLY[1:0] (RPDLY = 1 is shown)
* The number of NOPs is equal to ROWCOLDLY[2:0] (ROWCOLDLY = 1 is shown)
*** Clock suspended for 1 cycle when EBI is running at 1x and 1 or 2 cycles when EBI
is running at 2x, to enable sampling of data on the positive edge of the 1x clock.
CLK
CKE
CAS
RAS
DQM
BA[1:0]
A[11:0]
D
Clk
PER2
WE
CS
