297
8331B–AVR–03/12
Atmel AVR XMEGA AU
23.3.3
Double Speed Operation
Double speed operation allows for higher baud rates under asynchronous operation with lower
peripheral clock frequencies. When this is enabled, the baud rate for a given asynchronous baud
rate setting shown in
will be doubled. In this mode, the receiver will use
half the number of samples (reduced from 16 to 8) for data sampling and clock recovery. Due to
the reduced sampling, a more accurate baud rate setting and peripheral clock are required. See
”Asynchronous Data Reception” on page 301
for more details.
23.3.4
Synchronous Clock Operation
When synchronous mode is used, the XCK pin controls whether the transmission clock is input
(slave mode) or output (master mode). The corresponding port pin must be set to output for
master mode or to input for slave mode. The normal port operation of the XCK pin will be over-
ridden. The dependency between the clock edges and data sampling or data change is the
same. Data input (on RxD) is sampled at the XCK clock edge which is opposite the edge where
data output (TxD) is changed.
Figure 23-3.
Synchronous mode XCK timing.
Using the inverted I/O (INVEN) setting for the corresponding XCK port pin, the XCK clock edges
used for data sampling and data change can be selected. If inverted I/O is disabled (INVEN=0),
data will be changed at the rising XCK clock edge and sampled at the falling XCK clock edge. If
inverted I/O is enabled (INVEN=1), data will be changed at the falling XCK clock edge and sam-
pled at the rising XCK clock edge. For more details, see
.
23.3.5
Master SPI Mode Clock Generation
For master SPI mode operation, only internal clock generation is supported. This is identical to
the USART synchronous master mode, and the baud rate or BSEL setting is calculated using
the same equations (see
).
There are four combinations of the SPI clock (SCK) phase and polarity with respect to the serial
data, and these are determined by the clock phase (UCPHA) control bit and the inverted I/O pin
(INVEN) settings. The data transfer timing diagrams are shown in
.
Data bits are shifted out and latched in on opposite edges of the XCK signal, ensuring sufficient
time for data signals to stabilize. The UCPHA and INVEN settings are summarized in
. Changing the setting of any of these bits during transmission will corrupt both the
receiver and transmitter
RxD / TxD
XCK
RxD / TxD
XCK
UCPOL = 0
UCPOL = 1
Sample
Sample
