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8331B–AVR–03/12
Atmel AVR XMEGA AU
18.2.1
Clock Domains
The RTC is asynchronous, operating from a different clock source independently of the main
system clock and its derivative clocks, such as the peripheral clock. For control and count regis-
ter updates, it will take a number of RTC clock and/or peripheral clock cycles before an updated
register value is available in a register or until a configuration change has effect on the RTC.
This synchronization time is described for each register. Refer to
for selecting the asynchronous clock source for the RTC.
18.2.2
Interrupts and Events
The RTC can generate both interrupts and events. The RTC will give a compare interrupt and/or
event at the first count after the counter value equals the Compare register value. The RTC will
give an overflow interrupt request and/or event at the first count after the counter value equals
the Period register value. The overflow will also reset the counter value to zero.
Due to the asynchronous clock domain, events will be generated only for every third overflow or
compare match if the period register is zero. If the period register is one, events will be gener-
ated only for every second overflow or compare match. When the period register is equal to or
above two, events will trigger at every overflow or compare match, just as the interrupt request.
