312
8331B–AVR–03/12
Atmel AVR XMEGA AU
shift register and transmit buffer register do not contain data to be transmitted. When disabled,
the transmitter will no longer override the TxD port.
• Bit 2 – CLK2X: Double Transmission Speed
Setting this bit will reduce the divisor of the baud rate divider from16 to 8, effectively doubling the
transfer rate for asynchronous communication modes. For synchronous operation, this bit has
no effect and should always be written to zero. This bit must be zero when the USART commu-
nication mode is configured to IRCOM.
This bit is unused in master SPI mode operation.
• Bit 1 – MPCM: Multiprocessor Communication Mode
This bit enables the multiprocessor communication mode. When the MPCM bit is written to one,
the USART receiver ignores all the incoming frames that do not contain address information.
The transmitter is unaffected by the MPCM setting. For more detailed information, see
cessor Communication Mode” on page 307
.
This bit is unused in master SPI mode operation.
• Bit 0 – TXB8: Transmit Bit 8
TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames
with nine data bits. When used, this bit must be written before writing the low bits to DATA.
This bit is unused in master SPI mode operation.
23.15.5
CTRLC – Control register C
Note:
1. Master SPI mode
• Bits 7:6 – CMODE[1:0]: Communication Mode
These bits select the mode of operation of the USART as shown in
Notes:
1. See
”IRCOM - IR Communication Module” on page 316
for full description on using IRCOM
mode.
2. See
”USART in Master SPI Mode” on page 307
for full description of the master
SPI
operation.
Bit
7
6
5
4
3
2
1
0
+0x05
CMODE[1:0]
PMODE[1:0]
SBMODE
CHSIZE[2:0]
+0x05
CMODE[1:0]
–
–
–
UDORD
UCPHA
–
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
1
1
0
Table 23-7.
CMODE bit settings.
CMODE[1:0]
Group Configuration
Mode
00
ASYNCHRONOUS
Asynchronous USART
01
SYNCHRONOUS
Synchronous USART
10
IRCOM
IRCOM
11
MSPI
Master SPI
