429
8331B–AVR–03/12
Atmel AVR XMEGA AU
32.7
Register Description – PDI Control and Status Registers
The PDI control and status registers are accessible in the PDI control and status register space
(CSRS) using the LDCS and STCS instructions. The CSRS contains registers directly involved
in configuration and status monitoring of the PDI itself.
32.7.1
STATUS
–
Status register
• Bit 7:2
–
Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 1
–
NVMEN: Nonvolatile Memory Enable
This status bit is set when the key signalling enables the NVM programming interface. The exter-
nal programmer can poll this bit to verify successful enabling. Writing the NVMEN bit disables
the NVM interface.
• Bit 0
–
Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
32.7.2
RESET
–
Reset register
• Bit 7:0
–
RESET[7:0]: Reset Signature
When the reset signature, 0x59, is written to RESET, the device is forced into reset. The device
is kept in reset until RESET is written with a data value different from the reset signature. Read-
ing the lsb will return the status of the reset. The seven msbs will always return the value 0x00,
regardless of whether the device is in reset or not.
32.7.3
CTRL
–
Control register
• Bit 7:3
–
Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
Bit
7
6
5
4
3
2
1
0
–
–
–
–
–
–
NVMEN
–
STATUS
Read/Write
R
R
R
R
R
R
R/W
R
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
RESET[7:0]
RESET
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
–
–
–
–
–
GUARDTIME[2:0]
CTRL
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
