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8331B–AVR–03/12
Atmel AVR XMEGA AU
15. TC2 – 16-bit Timer/Counter Type 2
15.1
Features
•
A system of two eight-bit timer/counters
– Low-byte timer/counter
– High-byte timer/counter
•
Eight compare channels
– Four compare channels for the low-byte timer/counter
– Four compare channels for the high-byte timer/counter
•
Waveform generation
– Single slope pulse width modulation
•
Timer underflow interrupts/events
•
One compare match interrupt/event per compare channel for the low-byte timer/counter
•
Can be used with the event system for count control
•
Can be used to trigger DMA transactions
15.2
Overview
A timer/counter 2 is realized when a timer/counter 0 is set in split mode. It is a system of two
eight-bit timer/counters, each with four compare channels. This results in eight configurable
pulse width modulation (PWM) channels with individually controlled duty cycles, and is intended
for applications that require a high number of PWM channels.
The two eight-bit timer/counters in this system are referred to as the low-byte timer/counter and
high-byte timer/counter, respectively. The difference between them is that only the low-byte
timer/counter can be used to generate compare match interrupts, events and DMA triggers.
The two eight-bit timer/counters have a shared clock source and separate period and compare
settings. They can be clocked and timed from the peripheral clock, with optional prescaling, or
from the event system. The counters are always counting down.
The high resolution (hi-res) extension can be used to increase the waveform output resolution by
up to eight times by using an internal clock source running up to four times faster than the
peripheral clock.
The timer/counter 2 is set back to timer/counter 0 by setting it in normal mode; hence, one
timer/counter can exist only as either type 0 or type 2.
A detailed block diagram of the timer/counter 2 showing the low-byte (L) and high-byte (H)
timer/counter register split and compare modules is shown in
.
