337
8331B–AVR–03/12
Atmel AVR XMEGA AU
27.4
EBI Clock
The EBI is clocked from the Peripheral 2x (Clk
PER2
) Clock. This clock can run at the CPU Clock
frequency, or at two times the CPU Clock frequency. This can be used to lower the EBI access
time. Refer to
”System Clock and Clock Options” on page 82
for details the Peripheral 2x Clock
and how to configure this.
27.5
SRAM Configuration
When used with SRAM, the EBI can be configured with no multiplexing, or it can employ various
address multiplexing modes by using external address latches. When a limited number of pins
are available on the device for the EBI, address latch enable (ALE) signals are used to control
the external latches that multiplex address lines from the EBI. The available configurations are
shown in
”Multiplexing address byte 0, 1and 2” on page
describes the SRAM interface signals.
27.5.1
No Multiplexing
When no multiplexing is used, there is a one-to-one connection between the EBI and the SRAM.
No external address latches are used.
Figure 27-3.
Non-multiplexed SRAM connection.
27.5.2
Multiplexing address byte 0 and 1
When address byte 0 (A[7:0]) and address byte 1 (A[15:8]) are multiplexed, they are output from
the same port, and the ALE1 signal from the device controls the address latch.
Table 27-1.
SRAM Interface signals.
Signal
Description
CS
Chip Select
WE
Write Enable
RE
Read Enable
ALE[2:1]
Address Latch Enable
A[23:0]
Address
D[7:0]
Data bus
AD[7:0]
Combined Address and Data
EBI
SRAM
D[7:0]
A[7:0]
D[7:0]
A[7:0]
A[15:8]
A[21:16]
A[15:8]
A[21:16]
