89
8331B–AVR–03/12
Atmel AVR XMEGA AU
7.7
DFLL 2MHz and DFLL 32MHz
Two built-in digital frequency locked loops (DFLLs) can be used to improve the accuracy of the
2MHz and 32MHz internal oscillators. The DFLL compares the oscillator frequency with a more
accurate reference clock to do automatic run-time calibration of the oscillator and compensate
for temperature and voltage drift. The choices for the reference clock sources are:
• 32.768kHz calibrated internal oscillator
• 32.768kHz crystal oscillator connected to the TOSC pins
• External clock
• USB start of frame
The DFLLs divide the oscillator reference clock by 32 to use a 1.024kHz reference. The refer-
ence clock is individually selected for each DFLL, as shown on
.
Figure 7-6.
DFLL reference clock selection.
The ideal counter value representing the frequency ratio between the internal oscillator and a
1.024kHz reference clock is loaded into the DFLL oscillator compare register (COMP) during
reset. For the 32MHz oscillator, this register can be written from software to make the oscillator
run at a different frequency or when the ratio between the reference clock and the oscillator is
different (for example when the USB start of frame is used). The 48MHz calibration values must
be read from the production signature row and written to the 32MHz CAL register before the
DFLL is enabled with USB SOF as reference source.
32.768 kHz Crystal Osc
External Clock
32.768 kHz Int. Osc
DFLL32M
32 MHz Int. RCOSC
DFLL2M
2 MHz Int. RCOSC
clk
RC32MCREF
clk
RC2MCREF
TOSC1
TOSC2
XTAL1
DIV32
DIV32
XOSCSEL
USB Start of Frame
