Atmel AVR XMEGA AU series, Manual

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298
8331B–AVR–03/12
Atmel AVR XMEGA AU
The leading edge is the first clock edge of a clock cycle. The trailing edge is the last clock edge
of a clock cycle.
Figure 23-4. UCPHA and INVEN data transfer timing diagrams.
23.4 Frame Formats
Data transfer is frame based, where a serial frame consists of one character of data bits with
synchronization bits (start and stop bits) and an optional parity bit for error checking. Note that
this does not apply to master SPI operation (See
”SPI Frame Formats” on page 299 ). The
USART accepts all combinations of the following as valid frame formats:
• 1 start bit
• 5, 6, 7, 8, or 9 data bits
• no, even, or odd parity bit
• 1 or 2 stop bits
A frame starts with the start bit, followed by all the data bits (least-significant bit first and most-
significant bit last). If enabled, the parity bit is inserted after the data bits, before the first stop bit.
One frame can be directly followed by a start bit and a new frame, or the communication line can
return to the idle (high) state.
Figure 23-5 on page 299 illustrates the possible combinations of
frame formats. Bits inside brackets are optional.
Table 23-2. INVEN and UCPHA functionality.
SPI Mode INVEN UCPHA Leading Edge Trailing Edge
0 0 0 Rising, sample Falling, setup
1 0 1 Rising, setup Falling, sample
2 1 0 Falling, sample Rising, setup
3 1 1 Falling, setup Rising, sample
XCK
Data set u p (TXD)
Data sample (RXD)
XCK
Data set u p (TXD)
Data sample (RXD)
XCK
Data set u p (TXD)
Data sample (RXD)
XCK
Data set u p (TXD)
Data sample (RXD)
UCPOL=0 UCPOL=1
UCPHA=0
UCPHA=1