363
8331B–AVR–03/12
Atmel AVR XMEGA AU
28.7
Compare Function
The ADC has a built-in 12-bit compare function. The ADC compare register can hold a 12-bit
value that represents a threshold voltage. Each ADC channel can be configured to automatically
compare its result with this compare value to give an interrupt or event only when the result is
above or below the threshold.
All four ADC channels share the same compare register.
28.8
Starting a Conversion
Before a conversion is started, the input source must be selected for one or more ADC chan-
nels. An ADC conversion for a channel can be started either by the application software writing
to the start conversion bit for the channel or from any events in the event system. It is possible to
write the start conversion bit for several channels at the same time, or use one event to trigger
conversions on several channels at the same time. This makes it possible to scan several or all
channels from one event. The scan will start from the lowest channel number.
28.8.1
Input Source Scan
For ADC Channel 0 it is possible to select a range of consecutive input sources that is automati-
cally scanned and measured when a conversion is started. This is done by setting the first
(lowest) positive ADC channel input using the MUX control register, and a number of consecu-
tive positive input sources. When a conversion is started, the first selected input source is
measured and converted, then the positive input source selection is incremented after each con-
version until it reaches the specified number of sources to scan.
28.9
ADC Clock and Conversion Timing
The ADC is clocked from the peripheral clock. The ADC can prescale the peripheral clock to pro-
vide an ADC Clock (clk
ADC
) that matches the application requirements and is within the
operating range of the ADC.
Figure 28-12.
ADC prescaler.
The maximum ADC sample rate is given by the he ADC clock frequency (f
ADC
). The ADC can
sample a new measurement on every ADC clock cycle.
The propagation delay of an ADC measurement is given by:
9-bit ADC Prescaler
Clk
ADC
PRESCALER[2:0]
CL
K/4
CL
K/8
CL
K/1
6
CL
K/3
2
CL
K/6
4
CL
K/1
2
8
Clk
PER
CL
K/2
5
6
CL
K/5
1
2
Sample Rate
f
ADC
=
Propagation Delay =
1
RESOLUTION
2
---------------------------------------
GAIN
+
+
f
ADC
----------------------------------------------------------------------
