68
8331B–AVR–03/12
Atmel AVR XMEGA AU
• Bit 7:0 – TRFCNT[15:8]: Channel n Block Transfer Count register High
These bits hold the MSB of the 16-bit block transfer count.
The default value of this register is 0x1. If a user writes 0x0 to this register and fires a DMA trig-
ger, DMA will be doing 0xFFFF transfers.
5.14.7
REPCNT – Repeat Counter register
REPCNT counts how many times a block transfer is performed. For each block transfer, this reg-
ister will be decremented.
When repeat mode is enabled (see REPEAT bit in
”ADDRCTRL – Address Control register” on
), this register is used to control when the transaction is complete. The counter is decre-
mented after each block transfer if the DMA has to serve a limited number of repeated block
transfers. When repeat mode is enabled, the channel is disabled when REPCNT reaches zero
and the last block transfer is completed. Unlimited repeat is achieved by setting this register to
zero.
5.14.8
SRCADDR0 – Source Address 0
SRCADDR0, SRCADDR1, and SRCADDR2 represent the 24-bit value SRCADDR, which is the
DMA channel source address. SRCADDR2 is the most significant byte in the register.
SRCADDR may be automatically incremented or decremented based on settings in the SRCDIR
bits in
”ADDRCTRL – Address Control register” on page 63
• Bit 7:0 – SRCADDR[7:0]: Channel Source Address 0
These bits hold byte 0 of the 24-bit source address.
5.14.9
SRCADDR1 – Channel Source Address 1
• Bit 7:0 – SRCADDR[15:8]: Channel Source Address 1
These bits hold byte 1 of the 24-bit source address.
Bit
7
6
5
4
3
2
1
0
REPCNT[7:0]
REPCNT
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
SRCADDR[7:0]
SRCADDR0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
SRCADDR[15:8]
SRCADDR1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
