294
8331B–AVR–03/12
Atmel AVR XMEGA AU
Figure 23-1.
USART block diagram.
The clock generator includes a fractional baud rate generator that is able to generate a wide
range of USART baud rates from any system clock frequencies. This removes the need to use
an external crystal oscillator with a specific frequency to achieve a required baud rate. It also
supports external clock input in synchronous slave operation.
The transmitter consists of a single write buffer (DATA), a shift register, and a parity generator.
The write buffer allows continuous data transmission without any delay between frames.
The receiver consists of a two-level receive buffer (DATA) and a shift register. Data and clock
recovery units ensure robust synchronization and noise filtering during asynchronous data
reception. It includes frame error, buffer overflow, and parity error detection.
When the USART is set in master SPI mode, all USART-specific logic is disabled, leaving the
transmit and receive buffers, shift registers, and baud rate generator enabled. Pin control and
interrupt generation are identical in both modes. The registers are used in both modes, but their
functionality differs for some control settings.
An IRCOM module can be enabled for one USART to support IrDA 1.4 physical compliant pulse
modulation and demodulation for baud rates up to 115.2kbps. For details, refer to
Communication Module” on page 316
.
PARITY
GENERATOR
BSEL [H:L]
DATA
(Transmit)
CTRLA
CTRLB
CTRLC
BAUD RATE GENERATOR
FRACTIONAL DIVIDE
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER
RxD
TxD
PIN
CONTROL
DATA
(Receive)
PIN
CONTROL
XCK
DATA
RECOVERY
CLOCK
RECOVERY
PIN
CONTROL
TX
CONTROL
RX
CONTROL
PARITY
CHECKER
DA
T
A
BUS
OSC
SYNC LOGIC
Clock Generator
Transmitter
Receiver
