309
8331B–AVR–03/12
Atmel AVR XMEGA AU
23.15 Register Description
23.15.1
DATA – Data register
The USART transmit data buffer register (TXB) and USART receive data buffer register (RXB)
share the same I/O address and is referred to as USART data register (DATA). The TXB register
is the destination for data written to the DATA register location. Reading the DATA register loca-
tion returns the contents of the RXB register.
For 5-bit, 6-bit, or 7-bit characters, the upper unused bits will be ignored by the transmitter and
set to zero by the receiver.
The transmit buffer can be written only when DREIF in the STATUS register is set. Data written
to the DATA register when DREIF is not set will be ignored by the USART transmitter. When
data are written to the transmit buffer and the transmitter is enabled, the transmitter will load the
data into the transmit shift register when the shift register is empty. The data are then transmit-
ted on the TxD pin.
The receive buffer consists of a two-level FIFO. Always read STATUS before DATA in order to
get the correct status of the receive buffer.
23.15.2
STATUS – Status register
• Bit 7 – RXCIF: Receive Complete Interrupt Flag
This flag is set when there are unread data in the receive buffer and cleared when the receive
buffer is empty (i.e., does not contain any unread data). When the receiver is disabled, the
receive buffer will be flushed, and consequently RXCIF will become zero.
When interrupt-driven data reception is used, the receive complete interrupt routine must read
the received data from DATA in order to clear RXCIF. If not, a new interrupt will occur directly
after the return from the current interrupt. This flag can also be cleared by writing a one to its bit
location.
• Bit 6 – TXCIF: Transmit Complete Interrupt Flag
This flag is set when the entire frame in the transmit shift register has been shifted out and there
are no new data in the transmit buffer (DATA). TXCIF is automatically cleared when the transmit
complete interrupt vector is executed. The flag can also be cleared by writing a one to its bit
location.
Bit
7
6
5
4
3
2
1
0
RXB[[7:0]
TXB[[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
RXCIF
TXCIF
DREIF
FERR
BUFOVF
PERR
–
RXB8
STATUS
Read/Write
R
R/W
R
R
R
R
R
R/W
Initial Value
0
0
1
0
0
0
0
0
