Atmel AVR XMEGA AU series, Manual

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8331B–AVR–03/12
Atmel AVR XMEGA AU
23.16 Register Summary
23.16.1 Register Description - USART
23.16.2 Register Description - USART in SPI Master Mode
23.17 Interrupt Vector Summary
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 DATA DATA[7:0] 309
+0x01 STATUS RXCIF TXCIF DREIF FERR BUFOVF PERR – RXB8 309
+0x02 Reserved – – – – – – – –
+0x03 CTRLA – – RXCINTLVL[1:0] TXCINTLVL[1:0] DREINTLVL[1:0] 311
+0x04 CTRLB – – – RXEN TXEN CLK2X MPCM TXB8 311
CTRLC CMODE[1:0] PMODE[1:0] SBMODE CHSIZE[2:0] 312
+0x06 BAUDCTRLA BSEL[7:0] 314
+0x07 BAUDCTRLB BSCALE[3:0] BSEL[11:8] 314
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 DATA DATA[7:0] 309
+0x01 STATUS RXCIF TXCIF DREIF – – – – – 309
+0x02 Reserved – – – – – – – –
+0x03 CTRLA – – RXCINTLVL[1:0] TXCINTLVL[1:0] DREINTLVL[1:0] 311
+0x04 CTRLB – – – RXEN TXEN – – – 311
+0x05 CTRLC CMODE[1:0] – – – UDORD UCPHA – 312
+0x06 BAUDCTRLA BSEL[7:0] 314
+0x07 BAUDCTRLB BSCALE[3:0] BSEL[11:8] 314
Table 23-11. USART interrupt vectors and their word offset address.
Offset Source Interrupt Description
0x00 RXC_vect USART receive complete interrupt vector
0x02 DRE_vect USART data register empty interrupt vector
0x04 TXC_vect USART transmit complete interrupt vector