Atmel AVR XMEGA AU series, Manual

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8331B–AVR–03/12
Atmel AVR XMEGA AU
4.24 Register Summary – General Purpose I/O Registers
4.25 Register Summary – MCU Control
4.26 Interrupt Vector Summary – NVM Controller
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 GPIOR0 GPIOR[7:0] 46
+0x01 GPIOR1 GPIOR[7:0] 46
+0x02 GPIOR2 GPIOR[7:0] 46
+0x03 GPIOR3 GPIOR[7:0] 46
+0x04 GPIOR4 GPIOR[7:0] 46
+0x05 GPIOR5 GPIOR[7:0] 46
+0x06 GPIOR6 GPIOR[7:0] 46
+0x07 GPIOR7 GPIOR[7:0] 46
+0x08 GPIOR8 GPIOR[7:0] 46
+0x09 GPIOR9 GPIOR[7:0] 46
+0x0A GPIOR10 GPIOR[7:0] 46
+0x0B GPIOR11 GPIOR[7:0] 46
+0x0C GPIOR12 GPIOR[7:0] 46
+0x0D GPIOR13 GPIOR[7:0] 46
+0x0E GPIOR14 GPIOR[7:0] 46
+0x0F GPIOR15 GPIOR[7:0] 46
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 DEVID0 DEVID0[7:0] 47
+0x01 DEVID1 DEVID1[7:0] 47
+0x02 DEVID2 DEVID2[7:0] 47
+0x03 REVID – – – – REVID[3:0] 47
+0x04 JTAGUID JTAGUID[7:0] 48
+0x05 Reserved – – – – – – – –
+0x06 MCUCR – – – – – – – JTAGD 48
+0x07 ANAINIT – – – – STARTUPDLYB[1:0] STARTUPDLYA[1:0] 48
+0x08 EVSYSLOCK – – – EVSYS1LOC – – – EVSYS0LOCK 49
+0x09 AWEXLOCK – – – – – AWEXELOCK – AWEXCLOCK 49
+0x0A Reserved – – – – – – – –
+0x0B Reserved – – – – – – – –
Table 4-14. NVM interrupt vectors and their word offset address from the NVM controller interrupt base.
Offset Source Interrupt Description
0x00 EE_vect Nonvolatile memory EEPROM interrupt vector
0x02 SPM_vect Nonvolatile memory SPM interrupt vector