135
8331B–AVR–03/12
Atmel AVR XMEGA AU
request. The RET (subroutine return) instruction cannot be used when returning from the inter-
rupt handler routine, as this will not return the PMIC to its correct state.
Figure 12-1.
Interrupt controller overview
12.4
Interrupts
All interrupts and the reset vector each have a separate program vector address in the program
memory space. The lowest address in the program memory space is the reset vector. All inter-
rupts are assigned individual control bits for enabling and setting the interrupt level, and this is
set in the control registers for each peripheral that can generate interrupts. Details on each inter-
rupt are described in the peripheral where the interrupt is available.
All interrupts have an interrupt flag associated with it. When the interrupt condition is present,
the interrupt flag will be set, even if the corresponding interrupt is not enabled. For most inter-
rupts, the interrupt flag is automatically cleared when executing the interrupt vector. Writing a
logical one to the interrupt flag will also clear the flag. Some interrupt flags are not cleared when
executing the interrupt vector, and some are cleared automatically when an associated register
is accessed (read or written). This is described for each individual interrupt flag.
If an interrupt condition occurs while another, higher priority interrupt is executing or pending, the
interrupt flag will be set and remembered until the interrupt has priority. If an interrupt condition
occurs while the corresponding interrupt is not enabled, the interrupt flag will be set and remem-
bered until the interrupt is enabled or the flag is cleared by software. Similarly, if one or more
interrupt conditions occur while global interrupts are disabled, the corresponding interrupt flag
will be set and remembered until global interrupts are enabled. All pending interrupts are then
executed according to their order of priority.
Interrupts can be blocked when executing code from a locked section; e.g., when the boot lock
bits are programmed. This feature improves software security. Refer to
for details on lock bit settings.
Interrupts are automatically disabled for up to four CPU clock cycles when the configuration
change protection register is written with the correct signature. Refer to
for more details.
Peripheral 1
Interrupt Controller
INT REQ
INT LEVEL
INT REQ
INT LEVEL
CPU INT REQ
CTRL
LEVEL Enable
CPU.SREG
Global
Interrupt
Enable
Priority
decoder
STATUS
INTPRI
INT ACK
INT ACK
Peripheral n
INT LEVEL
INT REQ
INT ACK
CPU
CPU INT ACK
CPU ”RETI”
Sleep
Controller
Wake-up
