242
8331B–AVR–03/12
Atmel AVR XMEGA AU
Figure 20-7.
Clock generation configuration.
20.6
Ping-pong Operation
When an endpoint is configured for ping-pong operation, it uses the input and output data buf-
fers to create a single, double-buffered endpoint that can be set to input or output direction. This
provides double-buffered communication, as the CPU or DMA controller can access one of the
buffers, while the other buffer is processing an ongoing transfer. Ping-pong operation is identical
to the IN and OUT transactions described above, unless otherwise noted in this section. Ping-
pong operation is not possible for control endpoints.
When ping-pong operation is enabled for an endpoint, the endpoint in the opposite direction
must be disabled. The data buffer, data pointer, byte counter, and auxiliary data from the
enabled endpoint are used as bank 0, and, correspondingly, bank 1 for the opposite endpoint
direction.
The bank select (BANK) flag in the endpoint STATUS register indicates which data bank will be
u s e d i n t h e n e x t t r a n s a c t i o n . I t i s u p d a t e d a f t e r e a c h t r a n s a c t i o n . T h e
TRNCOMPL0/TRNCOMPL1, underflow/overflow (UDF/OVF), and CRC flags in the STATUS
register are set for either the enabled or the opposite endpoint direction according to the BANK
flag. The data toggle (TOGGLE), data buffer 0/1 not acknowledge (BUSNACK0 and
BUSNACK1), and BANK flags are updated for the enabled endpoint direction only.
USB module
48MHz full speed
6MHz for low speed
USBSRC
USB clock
prescaler
USBPSDIV
PLL
48MHz Internal Oscillator
