333
8331B–AVR–03/12
Atmel AVR XMEGA AU
26.7.4
CHECKSUM0 – Checksum Byte 0
CHECKSUM0, CHECKSUM1, CHECKSUM2, and CHECKSUM3 represent the 16- or 32-bit
CHECKSUM value and the generated CRC. The registers are reset to zero by default, but it is
possible to write RESET to reset all bits to one. It is possible to write these registers only when
the CRC module is disabled. If NVM is selected as the source, reading CHECKSUM will return a
zero value until the BUSY flag is cleared. If CRC-32 is selected and the BUSY flag is cleared
(i.e., CRC generation is completed or aborted), the bit reversed (bit 31 is swapped with bit 0, bit
30 with bit 1, etc.) and complemented result will be read from CHECKSUM. If CRC-16 is
selected or the BUSY flag is set (i.e., CRC generation is ongoing), CHECKSUM will contain the
actual content.
• Bit 7:0 – CHECKSUM[7:0]
These bits hold byte 0 of the generated CRC.
26.7.5
CHECKSUM1 – Checksum Byte 1
• Bit 7:0 – CHECKSUM[15:8]
These bits hold byte 1 of the generated CRC.
26.7.6
CHECKSUM2 – Checksum Byte 2
• Bit 7:0 – CHECKSUM[23:16]
These bits hold byte 2 of the generated CRC when CRC-32 is used.
26.7.7
CHECKSUM3 – CRC Checksum Byte 3
Bit
7
6
5
4
3
2
1
0
+0x04
CHECKSUM[7:0]
CHECKSUM0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
+0x05
CHECKSUM[15:8]
CHECKSUM1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
+0x06
CHECKSUM[23:16]
CHECKSUM2
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
+0x07
CHECKSUM[31:24]
CHECKSUM3
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
