128
8331B–AVR–03/12
Atmel AVR XMEGA AU
11. WDT – Watchdog Timer
11.1
Features
•
Issues a device reset if the timer is not reset before its timeout period
•
Asynchronous operation from dedicated oscillator
•
1kHz output of the 32kHz ultra low power oscillator
•
11 selectable timeout periods, from 8ms to 8s.
•
Two operation modes:
– Normal mode
– Window mode
•
Configuration lock to prevent unwanted changes
11.2
Overview
The watchdog timer (WDT) is a system function for monitoring correct program operation. It
makes it possible to recover from error situations such as runaway or deadlocked code. The
WDT is a timer, configured to a predefined timeout period, and is constantly running when
enabled. If the WDT is not reset within the timeout period, it will issue a microcontroller reset.
The WDT is reset by executing the WDR (watchdog timer reset) instruction from the application
code.
The window mode makes it possible to define a time slot or window inside the total timeout
period during which WDT must be reset. If the WDT is reset outside this window, either too early
or too late, a system reset will be issued. Compared to the normal mode, this can also catch sit-
uations where a code error causes constant WDR execution.
The WDT will run in active mode and all sleep modes, if enabled. It is asynchronous, runs from a
CPU-independent clock source, and will continue to operate to issue a system reset even if the
main clocks fail.
The configuration change protection mechanism ensures that the WDT settings cannot be
changed by accident. For increased safety, a fuse for locking the WDT settings is also available.
11.3
Normal Mode Operation
In normal mode operation, a single timeout period is set for the WDT. If the WDT is not reset
from the application code before the timeout occurs, then the WDT will issue a system reset.
There are 11 possible WDT timeout (TO
WDT
) periods, selectable from 8ms to 8s, and the WDT
can be reset at any time during the timeout period. A new WDT timeout period will be started
each time the WDT is reset by the WDR instruction. The default timeout period is controlled by
fuses. Normal mode operation is illustrated in
