Atmel AVR XMEGA AU series, Manual

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8331B–AVR–03/12
Atmel AVR XMEGA AU
• Bit 7:0 – DTLS: Dead-time Low Side
This register holds the number of peripheral clock cycles for the dead-time low side.
16.7.8 DTHS – Dead-time High Side register
• Bit 7:0 – DTHS: Dead-time High Side
This register holds the number of peripheral clock cycles for the dead-time high side.
16.7.9 DTLSBUF – Dead-time Low Side Buffer register
• Bit 7:0 – DTLSBUF: Dead-time Low Side Buffer
This register is the buffer for the DTLS register. If double buffering is used, valid content in this
register is copied to the DTLS register on an UPDATE condition.
16.7.10 DTHSBUF – Dead-time High Side Buffer register
• Bit 7:0 – DTHSBUF: Dead-time High Side Buffer
This register is the buffer for the DTHS register. If double buffering is used, valid content in this
register is copied to the DTHS register on an UPDATE condition.
16.7.11 OUTOVEN – Output Override Enable register
Note: 1. Can be written only if the fault detect flag (FDF) is zero.
Bit 7 6 5 4 3 2 1 0
+0x09 DTHS[7:0] DTHS
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
+0x0A DTLSBUF[7:0] DTLSBUF
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
+0x0B DTHSBUF[7:0] DTHSBUF
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
+0x0C OUTOVEN[7:0] OUTOVEN
Read/Write R/W
(1)
R/W
(1)
R/W
(1)
R/W
(1)
R/W
(1)
R/W
(1)
R/W
(1)
R/W
(1)
Initial Value 0 0 0 0 0 0 0 0