101
8331B–AVR–03/12
Atmel AVR XMEGA AU
• Bit 0 – RC2MCREF: 2MHz Oscillator Calibration Reference
This bit is used to select the calibration source for the 2MHz DFLL. By default, this bit is zero and
the 32.768kHz internal oscillator is selected. If this bit is set to one, the 32.768kHz crystal oscil-
lator on TOSC is selected as the reference. This bit will select only which calibration source to
use for the DFLL. In addition, the actual clock source that is selected must enabled and config-
ured for the calibration to function.
7.11
Register Description
–
DFLL32M/DFLL2M
7.11.1
CTRL – DFLL Control register
• Bit 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 0 – ENABLE: DFLL Enable
Setting this bit enables the DFLL and auto-calibration of the internal oscillator. The reference
clock must be enabled and stable before the DFLL is enabled.
After disabling the DFLL, the reference clock can not be disabled before the ENABLE bit is read
as zero.
7.11.2
CALA – DFLL Calibration Register A
The CALA and CALB registers hold the 13-bit DFLL calibration value that is used for automatic
run-time calibration of the internal oscillator. When the DFLL is disabled, the calibration registers
can be written by software for manual run-time calibration of the oscillator. The oscillators will
also be calibrated according to the calibration value in these registers when the DFLL is
disabled.
Table 7-10.
32MHz oscillator reference selection.
RC32MCREF[1:0]
Group Configuration
Description
00
RC32K
32.768kHz internal oscillator
01
XOSC32
32.768kHz crystal oscillator on TOSC
10
USBSOF
USB start of frame
11
—
Reserved
Bit
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
ENABLE
CTRL
Read/Write
R
R
R
R
R
R
R
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
–
CALA[6:0]
CALA
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
x
x
x
x
x
x
x
